Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY74FCT652T
SCCS032 - September 1994 - Revised March 2000
8-Bit Registered Transceiver
Functional Description
The FCT652T consists of bus transceiver circuits, D-type
鏗俰p-鏗俹ps, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the
internal storage registers. GAB and GBA control pins are
provided to control the transceiver functions. SAB and SBA
control pins are provided to select either real-time or stored
data transfer. The circuitry used for select control will eliminate
the typical decoding glitch that occurs in a multiplexer during
the transition between stored and real-time data. A LOW input
level selects real-time data and a HIGH selects stored data.
Data on the A or B data bus, or both, can be stored in the
internal D 鏗俰p-鏗俹ps by LOW-to-HIGH transitions at the
appropriate clock pins (CPAB or CPBA), regardless of the
select or enable control pins. When SAB and SBA are in the
real-time transfer mode, it is also possible to store data without
using the internal D-type 鏗俰p-鏗俹ps by simultaneously enabling
GAB and GBA. In this con鏗乬uration, each output reinforces its
input. Thus, when all other data sources to the two sets of bus
lines are at high impedance, each set of bus lines will remain
at its last state.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Features
鈥?Function, pinout, and drive compatible with FCT and
F logic
鈥?FCT-C speed at 5.4 ns max. (Com鈥檒)
FCT-A speed at 6.3 ns max. (Com鈥檒)
鈥?Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
鈥?Edge-rate control circuitry for signi鏗乧antly improved
noise characteristics
鈥?Power-off disable feature
鈥?Matched rise and fall times
鈥?Fully compatible with TTL input and output logic levels
鈥?Sink Current
64 mA
Source Current
32 mA
鈥?Independent register for A and B buses
鈥?Multiplexed real-time and stored data transfer
鈥?Extended commercial range of
鈭?0藲C
to +85藲C
Logic Block Diagram
CPBA
GAB
SBA
SAB
GBA
CPAB
B REG
1 OF 8 CHANNELS
Pin Configurations
LCC
Top View
A5
A4
NC
A3
A2
A1
A6
A
7
A
8
GND
NC
B
8
B
7
B
6
D
C
11 10 9 8 7 6 5
12
4
13
3
14
2
15
1
28
16
27
17
26
18
19 20 21 22 23 24 25
B5
B4
B3
NC
B2
B1
GBA
GAB
SAB
CPAB
NC
V
CC
CPBA
SBA
A
1
A REG
D
C
SOIC/QSOP
Top View
B
1
CPAB
SAB
GAB
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
TO 7 OTHER CHANNELS
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CPBA
SBA
GBA
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
8
Copyright
漏
2000, Texas Instruments Incorporated
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