CY54FCT574T, CY74FCT574T
8-BIT REGISTERS
WITH 3-STATE OUTPUTS
SCCS073 鈥?OCTOBER 2001
D
D
D
D
D
D
D
D
D
D
D
D
description
The 鈥橣CT574T devices are high-speed, low-power, octal D-type flip-flops, featuring separate D-type inputs for
each flip-flop. These devices have 3-state outputs for bus-oriented applications. A buffered clock (CP) and
output-enable (OE) inputs are common to all flip-flops. The 鈥橣CT574T are identical to 鈥橣CT374T, except for a
flow-through pinout to simplify board design. The eight flip-flops in the 鈥橣CT574T store the state of their
individual D inputs that meet the setup-time and hold-time requirements on the low-to-high CP transition. When
OE is low, the contents of the eight flip-flops are available at the outputs. When OE is high, the outputs are in
the high-impedance state. The state of OE does not affect the state of the flip-flops.
These devices are fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
錚?/div>
2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
D
7
GND
CP
O
7
O
6
Function, Pinout, and Drive Compatible
With FCT and F Logic
Reduced V
OH
(Typically = 3.3 V) Versions
of Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
I
off
Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?200-V Machine Model (A115-A)
鈥?1000-V Charged-Device Model (C101)
Edge-Triggered D-Type Inputs
250-MHz Typical Switching Rate
CY54FCT574T
鈥?32-mA Output Sink Current
鈥?12-mA Output Source Current
CY74FCT574T
鈥?64-mA Output Sink Current
鈥?32-mA Output Source Current
3-State Outputs
CY54FCT574T . . . D PACKAGE
CY74FCT574T . . . Q OR SO PACKAGE
(TOP VIEW)
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
O
0
O
O
2
O
3
O
4
O
5
O
6
O
7
CP
CY54FCT574T . . . L PACKAGE
(TOP VIEW)
OE
V
CC
D
1
D
0
D
2
D
3
D
4
D
5
D
6
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
O
0
O
1
O
2
O
3
O
4
O
5
1
1
2
3
4
5
6
7
8
