鈥?/div>
Fully compatible with TTL input and output logic levels
鈥?Sink Current
64 mA (Com鈥檒),
32 mA (Mil)
Source Current
32 mA (Com鈥檒),
12 mA (Mil)
Functional Description
The FCT377T has eight triggered D-type 鏗俰p-鏗俹ps with
individual D inputs. The common buffered clock inputs (CP)
loads all 鏗俰p-鏗俹ps simultaneously when the Clock Enable (CE)
is LOW. The register is fully edge-triggered. The state of each
D input, one set-up time before the LOW-to-HIGH clock
transition, is transferred to the corresponding 鏗俰p-鏗俹p鈥檚 O out-
put. The CE input must be stable only one set-up time prior to
the LOW-to-HIGH clock transition for predictable operation.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Logic Block Diagram
D
0
CE
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
CP
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
Pin Configurations
LCC
Top View
D3
D2
O2
O1
D1
Logic Symbol
SOIC/QSOP
Top View
CE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
D
0
CP
CE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
D
1
D
2
D
3
D
4
D
5
D
6
D
7
8
O
3
GND
CP
O
4
D
4
9
10
11
12
13
7 6 5 4
3
2
1
20
19
D
0
O
0
CE
V
CC
O
7
14 1516 17 18
D5
O5
O6
D6
D7
Copyright
漏
2000, Texas Instruments Incorporated