Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY74FCT163501
CY74FCT163H501
SCCS047 - January 1998 - Revised March 2000
18-Bit Registered Transceivers
鈥?Eliminates the need for external pull-up or pull-down
resistors
Features
鈥?Low power, pin-compatible replacement for LCX and
LPT families
鈥?5V tolerant inputs and outputs
鈥?24 mA balanced drive outputs
鈥?Power-off disable outputs permits live insertion
鈥?Edge-rate control circuitry for reduced noise
鈥?FCT-C speed at 4.6 ns
鈥?Latch-up performance exceeds JEDEC standard no. 17
鈥?ESD > 2000V per MIL-STD-883D, Method 3015
鈥?Typical output skew < 250ps
鈥?Industrial temperature range of 鈥?0藲C to +85藲C
鈥?TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
鈥?Typical V
olp
(ground bounce) performance exceeds Mil
Std 883D
鈥?V
CC
= 2.7V to 3.6V
Functional Description
These 18-bit universal bus transceivers can be operated in
transparent, latched or clock modes by combining D-type
latches and D-type 鏗俰p-鏗俹ps. Data 鏗俹w in each direction is
controlled by output enable (OEAB and OEBA), latch enable
(LEAB and LEBA), and clock inputs (CLKAB and CLKBA). For
A-to-B data 鏗俹w, the device operates in transparent mode
when LEAB is HIGH. When LEAB is LOW, the A data is
latched if CLKAB is held at a HIGH or LOW logic level. If LEAB
is LOW, the A bus data is stored in the latch/鏗俰p-鏗俹p on the
LOW-to-HIGH transition of CLKAB. OEAB performs the output
enable function on the B port. Data 鏗俹w from B-to-A is similar
to that of A-to-B and is controlled by OEBA, LEBA, and
CLKBA. The output buffers are designed with a power-off
disable feature to allow live insertion of boards.
THE CY74FCT163501 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors, as well as provides for
minimal undershoot and reduced ground bounce. The
CY74FCT163501 is ideal for driving transmission lines.
The CY74FCT163H501 is a 24-mA balanced output part, that
has 鈥渂us hold鈥?on the data inputs. The device retains the
input鈥檚 last state whenever the input goes to high impedance.
This eliminates the need for pull-up/down resistors and
prevents 鏗俹ating inputs.
CY74FCT163501 Features:
鈥?Balanced output drivers: 24 mA
鈥?Reduced system switching noise
鈥?Typical V
OLP
(ground bounce) <0.6V at V
CC
= 3.3V,
T
A
= 25藲C
CY74FCT163H501 Features:
鈥?Bus hold retains the last active state
鈥?Devices with bus hold are not recommended for trans-
lating rail-to-rail CMOS signals to 3.3V logic levels
Functional Block Diagram; CY74FCT163501, CY74FCT163H501
Pin Configuration
SSOP/TSSOP
Top View
OEAB
LEAB
A
1
GND
A
2
A
3
V
CC
A
4
A
5
A
6
GND
A
7
A
8
A
9
A
10
A
11
A
12
GND
A
13
A
14
A
15
V
CC
A
16
A
17
GND
A
18
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B
1
GND
B
2
B
3
V
CC
B
4
B
5
B
6
GND
B
7
B
8
B
9
B
10
B
11
B
12
GND
B
13
B
14
B
15
V
CC
B
16
B
17
GND
B
18
CLKBA
GND
FCT163501-2
OEAB
CLKBA
LEBA
OEBA
CLKAB
LEAB
C
C
D
A
1
D
B
1
C
D
C
D
TO 17 OTHER CHANNELS
FCT163501-1
Copyright
漏
2000, Texas Instruments Incorporated
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