1CY74FCT163952
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY74FCT163952
CY74FCT163H952
SCCS048 - March 1997 - Revised March 2000
16-Bit Registered Transceivers
Functional Description
These 16-bit registered transceivers are high-speed,
low-power devices. 16-bit operation is achieved by connecting
the control lines of the two 8-bit registered transceivers
together. For data 鏗俹w from bus A-to-B, CEAB must be LOW
to allow data to be stored when CLKAB transitions from
LOW-to-HIGH. The stored data will be present on the output
when OEAB is LOW. Control of data from B-to-A is similar and
is controlled by using the CEBA, CLKBA, and OEBA inputs.
The outputs are 24-mA balanced output drivers with current
limiting resistors to reduce the need for external terminating
resistors and provide for minimal undershoot and reduced
ground bounce.
The CY74FCT163H952 has 鈥渂us hold鈥?on the data inputs,
which retains the input鈥檚 last state whenever the source driving
the input goes to high impedance. This eliminates the need for
pull-up/down resistors and prevents 鏗俹ating inputs.
The CY74FCT163952 is designed with inputs and outputs
capable of being driven by 5.0V buses, allowing its use in
mixed voltage systems as a translator. The outputs are also
designed with a power off disable feature enabling its use in
applications requiring live insertion.
Features
鈥?Low power, pin-compatible replacement for LCX and
LPT families
鈥?5V tolerant inputs and outputs
鈥?24 mA balanced drive outputs
鈥?Power-off disable outputs permits live insertion
鈥?Edge-rate control circuitry for reduced noise
鈥?FCT-C speed at 4.4 ns
鈥?Latch-up performance exceeds JEDEC standard no. 17
鈥?Typical output skew < 250 ps
鈥?Industrial temperature range of 鈥?0藲C to +85藲C
鈥?TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
鈥?Typical
V
olp
(ground bounce) performance exceeds Mil
Std 883D
鈥?V
CC
= 2.7V to 3.6V
鈥?ESD (HBM) > 2000V
CY74FCT163H952
鈥?Bus hold on data inputs
鈥?Eliminates the need for external pull-up or pull-down
resistors
鈥?Devices with bus hold are not recommended for trans-
lating rail-to-rail CMOS signals to 3.3V logic levels
Logic Block Diagrams; CY74FCT163952, CY74FCT163H952
1
CEBA
1
CLKBA
1
OEAB
1
CEAB
1
CLKAB
1
OEBA
1
A
1
2
CEBA
2
CLKBA
2
OEAB
2
CEAB
2
CLKAB
2
OEBA
Pin Configuration
SSOP/TSSOP
Top View
1
OEAB
1
CLKAB
1
CEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OEBA
1
CLKBA
1
CEBA
GND
1
A
1
1
A
2
V
CC
1
A
3
1
A
4
1
A
5
2
B
1
GND
1
B
1
1
B
2
V
CC
1
B
3
1
B
4
1
B
5
C
CE
D
C
CE
D
1
B
1
2
A
1
C
CE
D
C
CE
D
GND
1
A
6
1
A
7
1
A
8
2
A
1
2
A
2
2
A
3
GND
1
B
6
1
B
7
1
B
8
2
B
1
2
B
2
2
B
3
TO7 OTHERCHANNELS
TO7 OTHERCHANNELS
GND
2
A
4
2
A
5
2
A
6
V
CC
2
A
7
2
A
8
GND
2
B
4
2
B
5
2
B
6
V
CC
2
B
7
2
B
8
GND
2
CEAB
2
CLKAB
2
OEAB
GND
2
CEBA
2
CLKBA
2
OEBA
Copyright
漏
2000, Texas Instruments Incorporated
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3
4
5
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