1CY74FCT163646
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY74FCT163646
SCCS058 - March 1997 - Revised March 2000
16-Bit Registered Transceiver
Functional Description
The CY74FCT163646 16-bit transceiver is a three-state,
D-type register, and control circuitry arranged for multiplexed
transmission of data directly from the input bus or from the
internal registers. Data on the A or B bus will be clocked into
the registers as the appropriate clock pin goes to a HIGH logic
level. Output Enable (OE) and direction pins (DIR) are
provided to control the transceiver function. In the transceiver
mode, data present at the high impedance port may be stored
in either the A or B register, or in both. The select controls can
multiplex stored and real-time (transparent mode) data. The
direction control determines which bus will receive data when
the Output Enable (OE) is Active LOW. In the isolation mode
(Output Enable (OE) HIGH), A data may be stored in the B
register and/or B data may be stored in the A register.
The CY74FCT163646 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The inputs
and outputs were designed to be capable of being driven by
5.0V buses, allowing them to be used in mixed voltage
systems as translators. The outputs are also designed with a
power-off disable feature enabling them to be used in
applications requiring live insertion.
Features
鈥?Low power, pin-compatible replacement for LCX and
LPT families
鈥?5V tolerant inputs and outputs
鈥?24 mA balanced drive outputs
鈥?Power-off disable outputs permits live insertion
鈥?Edge-rate control circuitry for reduced noise
鈥?FCT-C speed at 5.4 ns
鈥?Latch-up performance exceeds JEDEC standard no. 17
鈥?ESD > 2000V per MIL-STD-883D, Method 3015
鈥?Typical output skew < 250 ps
鈥?Industrial temperature range of 鈥?0藲C to +85藲C
鈥?TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
鈥?Typical V
olp
(ground bounce) performance exceeds Mil
Std 883D
鈥?V
CC
= 2.7V to 3.6V
Logic Block Diagrams
1OE
1DIR
1CLKBA
1SBA
1CLKAB
1SAB
B REG
D
C
2OE
2DIR
2CLKBA
2SBA
2CLKAB
2SAB
B REG
D
C
1A1
A REG
D
C
1B1
2A1
A REG
D
C
2B1
TO 7 OTHER CHANNELS
TO 7 OTHER CHANNELS
Copyright
漏
2000, Texas Instruments Incorporated
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