1CY74FCT163543
Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY74FCT163543
SCCS063A - June 1997 - Revised April 2000
16-Bit Latched Transceiver
Functional Description
The CY74FCT163543 is a 16-bit, high-speed, low power latched
transceiver that is organized as two independent 8-bit D-type latched
transceivers, containing two sets of eight D-type latches with separate
Latch Enable (LEAB, LEAB) and Output Enable (OEAB, OEAB) con-
trols for each set to permit independent control of inputting and out-
putting in either direction of data flow. For data flow from A to B, for
example, the A-to-B input Enable (CEAB) must be LOW in order to
enter data from A or to take data from B, as indicated in the truth table.
With CAEB LOW, a LOW signal on the A-to-B Latch Enable (LEAB)
makes the A-to-B latches transparent; a subsequent LOW-to-HIGH
transition of the LEAB signal puts the A latches in the storage mode
and their outputs no longer follow the A inputs. With CEAB and OEAB
both LOW, the three-state B output buffers are active and reflect the
data present at the output of the A latches. Control of data from B to
A is similar, but uses CEAB, LEAB, and OEAB inputs.
The CY74FCT163543 has 24-mA balanced output drivers
with current limiting resistors in the outputs. This reduces the
need for external terminating resistors and provides for
minimal undershoot and reduced ground bounce. The inputs
and outputs are capable of being driven by 5.0V buses, allow-
ing them to be used in mixed voltage systems as translators.
The outputs are also designed with a power off disable feature
enabling them to be used in applications requiring live inser-
tion. Flow-through pinout and small shrink packaging simplify board
design.
Features
鈥?Low power, pin-compatible replacement for LCX and
LPT families
鈥?5V tolerant inputs and outputs
鈥?24 mA balanced drive outputs
鈥?Power-off disable outputs permits live insertion
鈥?Edge-rate control circuitry for reduced noise
鈥?FCT-C speed at 5.1 ns
鈥?Latch-up performance exceeds JEDEC standard no. 17
鈥?ESD > 2000V per MIL-STD-883D, Method 3015
鈥?Typical output skew < 250 ps
鈥?Industrial temperature range of 鈥?0藲C to +85藲C
鈥?TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
鈥?Typical V
olp
(ground bounce) performance exceeds Mil
Std 883D
鈥?V
CC
= 2.7V to 3.6V
Logic Block Diagrams
1
OEBA
1
CEBA
1
LEBA
1
OEAB
1
CEAB
1
LEAB
1
A
1
Pin Configuration
Top View
SSOP/TSSOP
1
OEAB
1
LEAB
1
CEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OEBA
1
LEBA
1
CEBA
C
D
C
D
GND
1
A
1
1
B
1
1
A
2
V
CC
1
A
3
1
A
4
1
A
5
GND
1
A
6
1
A
7
1
A
8
2
A
1
2
A
2
2
A
3
GND
2
A
4
2
A
5
2
A
6
GND
1
B
1
1
B
2
V
CC
1
B
3
1
B
4
1
B
5
GND
1
B
6
1
B
7
1
B
8
2
B
1
2
B
2
2
B
3
TO 7 OTHER CHANNELS
2
OEBA
2
CEBA
2
LEBA
2
OEAB
2
CEAB
2
LEAB
2
A
1
GND
2
B
4
2
B
5
2
B
6
C
D
C
D
2
B
1
V
CC
2
A
7
2
A
8
GND
2
CEAB
2
LEAB
2
OEAB
V
CC
2
B
7
2
B
8
GND
2
CEBA
2
LEBA
2
OEBA
TO 7 OTHER CHANNELS
Copyright
漏
2000, Texas Instruments Incorporated
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