Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY74FCT163244
CY74FCT163H244
SCCS046 - December 1996 - Revised March 2000
16-Bit Buffers/Line Drivers
CY74FCT163H244
鈥?Bus hold on data inputs
鈥?Eliminates the need for external pull-up or pull-down
resistors
鈥?Devices with bus hold are not recommended for trans-
lating rail-to-rail CMOS signals to 3.3V logic levels
Features
鈥?Low power, pin-compatible replacement for LCX and
LPT families
鈥?5V tolerant inputs and outputs
鈥?24 mA balanced drive outputs
鈥?Power-off disable outputs permits live insertion
鈥?Edge-rate control circuitry for reduced noise
鈥?FCT-C speed at 4.1 ns
鈥?Latch-up performance exceeds JEDEC standard no. 17
鈥?Typical output skew < 250 ps
鈥?Industrial temperature range of 鈥?0藲C to +85藲C
鈥?TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)
鈥?Typical
V
olp
(ground bounce) performance exceeds Mil
Std 883D
鈥?V
CC
= 2.7V to 3.6V
鈥?ESD (HBM) > 2000V
Functional Description
These 16-bit buffers/line drivers are designed for use in
memory driver, clock driver, or other bus interface applications,
where high-speed and low power are required. The three-state
controls are designed to allow 4-bit, 8-bit or combined 16-bit
operation. Flow-through pinout and small shrink packaging
simpli鏗乪s board layout.
The CY74FCT163244 has 24-mA balanced output drivers
with current limiting resistors in the outputs.
The CY74FCT163H244 has 鈥渂us hold鈥?on the data inputs,
which retains the last state of the input whenever the source
driving the input goes to high impedance. This eliminates the
need for pull-up/down resistors and prevents 鏗俹ating inputs.
Logic Block Diagrams CY74FCT163244, CY74FCT163H244
1
OE
3
OE
Pin Configuration
SSOP/TSSOP
Top View
1
OE
1
2
3
4
5
48
47
46
45
44
2
OE
1
A
1
1
A
2
1
A
1
1
Y
1
3
A
1
3
Y
1
1
Y
1
1
Y
2
1
A
2
1
Y
2
3
A
2
GND
3
Y
2
1
Y
3
1
Y
4
V
CC
2
Y
1
2
Y
2
3
Y
4
GND
1
A
3
1
A
4
1
A
3
1
Y
3
3
A
3
3
Y
3
163244
6 163H244 43
42
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
V
CC
2
A
1
2
A
2
1
A
4
1
Y
4
3
A
4
GND
2
Y
3
2
Y
4
3
Y
1
GND
2
A
3
2
A
4
3
A
1
3
A
2
2
OE
4
OE
3
Y
2
GND
2
A
1
2
Y
1
4
A
1
4
Y
1
3
Y
3
3
Y
4
V
CC
4
Y
1
4
Y
2
2
A
3
2
Y
3
4
A
3
4
Y
3
GND
3
A
3
3
A
4
2
A
2
2
Y
2
4
A
2
4
Y
2
V
CC
4
A
1
4
A
2
GND
4
Y
3
4
Y
4
4
OE
GND
4
A
3
4
A
4
3
OE
2
A
4
2
Y
4
4
A
4
4
Y
4
Copyright
漏
2000, Texas Instruments Incorporated
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2
3
4
5
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