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CY54FCT841ATDMB Datasheet

  • CY54FCT841ATDMB

  • 10-Bit Latch

  • 8頁

  • TI

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Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY54/74FCT841T
SCCS035 - September 1994 - Revised March 2000
10-Bit Latch
鈥?/div>
High-speed parallel latches
鈥?/div>
Buffered common latch enable input
Features
鈥?Function, pinout, and drive compatible with FCT, F, and
AM29841 logic
鈥?FCT-C speed at 5.5 ns max. (Com鈥檒)
FCT-B speed at 6.5 ns max. (Com鈥檒)
鈥?Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
鈥?Edge-rate control circuitry for signi鏗乧antly improved
noise characteristics
鈥?Power-off disable feature
鈥?/div>
Matched rise and fall times
鈥?/div>
ESD > 2000V
鈥?Fully compatible with TTL input and output logic levels
鈥?/div>
Sink current
64 mA (Com鈥檒),
32 mA (Mil)
Source current 32 mA (Com鈥檒),
12 mA (Mil)
Functional Description
The FCT841T bus interface latch is designed to eliminate the
extra packages required to buffer existing latches and provide
extra data width for wider address/data paths or buses
carrying parity. The FCT841T is a buffered 10-bit wide version
of the FCT373 function.
The FCT841T high-performance interface is designed for
high-capacitance load drive capability while providing
low-capacitance bus loading at both inputs and outputs.
Outputs are designed for low-capacitance bus loading in the
high impedance state and are designed with a power-off
disable feature to allow for live insertion of boards.
Functional Block Diagram
D
0
D
1
D
2
D
3
D
4
D
5
D
N- 1
D
N
D
LE
Q
D
LE
Q
Q
D
LE
Q
Q
D
LE
Q
Q
D
LE
Q
Q
D
LE
Q
Q
D
LE
Q
Q
D
LE
Q
Q
LE
OE
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
N- 1
Y
N
Logic Block Diagram
D
10
D
LE
LE
OE
Q
10
Pin Configurations
DIP/QSOP/SOIC
Top View
Y
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
LE
Copyright
漏
2000, Texas Instruments Incorporated

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