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CY38030 Datasheet

  • CY38030

  • Programmable Logic

  • 660.73KB

  • 45頁

  • ETC

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USE DELTA39K鈩?FOR
Quantum38K鈩?ISR鈩?/div>
ALL NEW DESIGNS
CPLD Family
CPLDs Designed for Migration
Features
鈥?High density
鈥?30K to 100K usable gates
鈥?512 to 1536 macrocells
鈥?136 to 302 maximum I/O pins
鈥?Eight dedicated inputs including four clock pins and
four global I/O control signal pins; four JTAG inter-
face pins for reconfigurability/boundary scan
鈥?Embedded memory
鈥?16-Kb to 48-Kb embedded dual-port channel memo-
ry
鈥?125-MHz in-system operation
鈥?AnyVolt鈩?interface
鈥?3.3V and 2.5V V
CC
operation
鈥?3.3V, 2.5V and 1.8V I/O capability
鈥?Low-power operation
鈥?0.18-mm 6-layer metal SRAM-based logic process
鈥?Full-CMOS implementation of product term array
鈥?Simple timing model
鈥?No penalty for using full 16 product terms/macrocell
鈥?No delay for single product term steering or sharing
鈥?Flexible clocking
鈥?Four synchronous clocks per device
鈥?Locally generated product term clock
鈥?Clock polarity control at each register
鈥?Carry-chain logic for fast and efficient arithmetic opera-
tions
鈥?Multiple I/O standards supported
鈥?LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI
鈥?Compatible with NoBL鈩? ZBT鈩? and QDR鈩?SRAMs
鈥?Programmable slew rate control on each I/O pin
鈥?User-programmable Bus Hold capability on each I/O pin
鈥?Fully 3.3V PCI-compliant (as per PCI spec rev. 2.2)
鈥?Compact PCI hot swap ready
鈥?Multiple package/pinout offering across all densities
鈥?208 to 484 pins in PQFP and FBGA packages
鈥?Simplifies design migration across density
鈥?In-System Reprogrammable鈩?(ISR鈩?
鈥?JTAG-compliant on-board configuration
鈥?Design changes do not cause pinout changes
鈥?IEEE1149.1 JTAG boundary scan
鈥?Pin-to-pin-compatible with Cypress鈥檚 high-end
Delta39K鈩?CPLDs allowing easy migration path to
鈥?More embedded memory
鈥?Spread Aware鈩?PLL
鈥?Higher density and higher speed devices
鈥?High speed I/O standards and more
Development Software
鈥?/div>
Warp
廬
鈥?IEEE 1076/1164 VHDL or IEEE 1364 Verilog context
sensitive editing
鈥?Active-HDL FSM graphical finite state machine editor
鈥?Active-HDL SIM post-synthesis timing simulator
鈥?Architecture Explorer for detailed design analysis
鈥?Static Timing Analyzer for critical path analysis
鈥?/div>
Available on Windows 98鈩? Windows NT鈩?
Windows ME鈩? Windows 2000鈩? and Sun Solaris錚?/div>
2.5 and later for $99
鈥?/div>
Supports all Cypress programmable logic products
Quantum38K錚?ISR CPLD Family Members
Channel
memory
(Kb)
16
24
48
Maximum I/O
Pins
174
218
302
f
MAX2
(MHz)
125
125
125
Speed 鈥?t
PD
Pin-to-Pin
(ns)
10
10
10
Standby I
CC
[2]
T
A
=25脳C
3.3/2.5V
5 mA
5 mA
10 mA
Device
38K30
38K50
38K100
Typical Gates
[1]
16K鈥?8K
23K鈥?2K
46K鈥?44K
Macrocells
512
768
1536
Notes:
1. Upper limit of typical gates is calculated by assuming that only 50% of the channel memory is used.
2. Standby I
CC
values are with no output load and stable inputs.
Cypress Semiconductor Corporation
Document #: 38-03043 Rev. *G
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised April 18, 2003

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