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CY2V995AIT Datasheet

  • CY2V995AIT

  • S2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer

  • 283.10KB

  • 10頁(yè)

  • CYPRESS

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CY2V995
2.5/3.3V 200-MHz Multi-Output
Zero Delay Buffer
Features
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2.5V or 3.3V operation
Split output bank power supplies
Output frequency range: 6 MHz to 200 MHz
Output-output skew: < 150 ps
Cycle-cycle jitter: < 100 ps
Selectable positive or negative edge synchronization
8 LVTTL outputs driving 50鈩?terminated lines
LVCMOS/LVTTL over-voltage tolerant reference input
Selectable phase-locked loop (PLL) frequency range
and lock indicator
(1-6,8,10,12)x multiply and (1/2,1/4)x divide ratios
Spread-Spectrum-compatible
Power-down mode
Industrial temperature range: 鈥?0擄C to +85擄C
44-pin TQFP package
Description
The CY2V995 is a low-voltage, low-power, eight output,
200-MHz clock driver. It features function necessary to
optimize the timing of high-performance computer and
communication systems.
The user can program the frequency of the output banks
through nF[0:1] and DS[0:1] pins. Any one of the outputs can
be connected to feedback input to achieve different reference
frequency multiplication and divide ratios and zero
input-output delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the PE pin controls the synchro-
nization of the output signals to either the rising or the falling
edge of the reference clock.
Block Diagram
TEST
PD#
PE
FS VDDQ1
Pin Configuration
PLL
FB
DS1:0
LOCK
/N
3
3
4F1
1Q0
1F1:0
1Q1
sOE#
PD#
PE
VDDQ4
VDDQ4
4Q1
4Q0
VSS
VSS
VSS
2Q0
2F1:0
2Q1
3F1:0
3
3
/K
3Q0
3Q1
VDDQ3
1
2
3
4
5
6
7
8
9
10
11
12 13 14 15 16 17 18 19 20 2122
4F0
44 43 42 41 40 39 38 37 36 35 34
33
32
31
30
29
28
27
26
25
24
23
1F0
DS1
DS0
LOCK
VDDQ1
VDDQ1
1Q0
1Q1
VSS
VSS
VSS
4F1:0
3
3
/M
4Q0
4Q1
VDDQ4 sOE#
Cypress Semiconductor Corporation
Document #: 38-07435 Rev. *A
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3901 North First Street
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San Jose
,
CA 95134
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408-943-2600
Revised January 19, 2004
VSS
3Q1
3Q0
VDDQ3
VDDQ3
FB
VDD
VDDQ1
2Q1
2Q0
VSS
3F1
3F0
REF
CY2V995
FS
VDD
REF
VSS
TEST
2F1
2F0
1F1
3
3

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