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CY2DP818ZIT Datasheet

  • CY2DP818ZIT

  • 1:8 Clock Fanout Buffer

  • 8頁

  • CYPRESS

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ComLink鈩?Series
CY2DP818
1:8 Clock Fanout Buffer
Features
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Low-voltage operation V
DD
= 3.3V
1:8 fanout
Single-input-configurable for LVDS, LVPECL, or LVTTL
8 pair of LVPECL outputs
Drives a 50-ohm load
Low input capacitance
Low output skew
Low propagation delay Typical
(tpd < 4 ns)
Industrial versions available
Package available include: TSSOP
Does not exceed Bellcore 802.3 standards
Operation at
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350 MHz鈥?00 Mbps
Description
This Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industry鈥檚 fastest logic.
The Cypress CY2DP818 fanout buffer features a single LVDS
or a single-ended LVTTL-compatible input and eight LVPECL
output pairs.
Designed for data-communications clock-management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
The CY2DP818 is ideal for both level translations from
single-ended to LVPECL and/or for the distribution of
LVPECL-based clock signals.
The Cypress CY2DP818 has configurable input functions. The
input is user configurable via the Inconfig pin for single ended
or differential input.
Block Diagram
Q1A
Q1B
Pin Configuration
Q2A
Q2B
INPUT
(LVPECL / LVDS / LVTTL)
Q4A
INPUT A
INPUT B
Q4B
Q5A
CY2DP818
Q3A
Q3B
InConfig
Q5B
Q6A
Q6B
Q7A
Q7B
GND
VDD
VDD
VDD
VDD
VDD
InConfig
VDD
GND
INPUT A
INPUT B
GND
VDD
VDD
VDD
VDD
VDD
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
GND
Q1A
Q1B
Q2A
Q2B
Q3A
Q3B
Q4A
Q4B
VDD
Q5A
Q5B
Q6A
Q6B
Q7A
Q7B
Q8A
Q8B
GND
Q8A
Q8B
38-pin TSSOP
OUTPUT
(LVPECL)
Cypress Semiconductor Corporation
Document #: 38-07061 Rev. *A
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3901 North First Street
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San Jose
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CA 95134
鈥?408-943-2600
Revised July 9, 2002

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