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CY2CC910OC Datasheet

  • CY2CC910OC

  • 1:10 Clock Fanout Buffer

  • 8頁

  • CYPRESS

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COMLINK鈩?SERIES
CY2CC910
1:10 Clock Fanout Buffer
Features
鈥?Low-voltage operation
鈥?Full-range support:
鈥?3.3V
鈥?2.5V
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?1.8V
Over voltage tolerant input hot swappable
1:10 fanout
Drives either a 50-Ohm or 75-Ohm load
Low-input capacitance
Low-output skew
Low-propagation delay
Typical (tpd < 4 ns)
High-speed operation:
鈥?-200 MHz@1.8V
鈥?650 MHz@2.5V/3.3V
鈥?Industrial versions available
鈥?Available packages include: SOIC, SSOP
Description
The Cypress series of network circuits are produced using
advanced 0.35 micron CMOS technology, achieving the indus-
tries fastest logic and buffers.
The Cypress CY2CC910 fanout buffer features one input and
ten outputs. Ideal for conversion from/to 3.3V/2.5V/1.8V
Designed for Data Communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
Cypress employs unique AVCMOS type outputs VOI鈩?/div>
(Variable Output Impedance) that dynamically adjust for
variable impedance matching and eliminate the need for
series damping resistors and reduce noise overall.
Block Diagram
3
Pin Configuration
Q1
IN
5
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q 10
OUTPUT
(AVCMOS)
GND
Q1
VDD
Q2
GND
Q3
VDD
Q4
GND
VDD
4 ,8
1 5 ,2 0
IN
1
7
9
11
INPUT
(AVCMOS)
2 ,6 ,1 0
1 3 ,1 7
12
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
Q10
Q9
GND
Q8
VDD
Q7
GND
Q6
Q5
14
20 pin SOIC/SSOP
GND
16
18
19
Pin Description
Pin Number
1
2,6,10,13,17
4,8,15,20
3,5,7,9,11,12,14,16,18,19
Cypress Semiconductor Corporation
Document #: 38-07348 Rev. *A
IN
Pin Name
Input
Ground
Power Supply
Output
鈥?/div>
CA 95134 鈥?408-943-2600
Revised October 3, 2002
Description
G
ND
V
DD
Q1,Q2,Q3,Q4,Q5,Q6,Q7,Q8,Q9,Q10
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
CY2CC910

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