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CY2CC810OI Datasheet

  • CY2CC810OI

  • 1:10 Clock Fanout Buffer

  • 7頁(yè)

  • CYPRESS

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COMLINK鈩?SERIES
CY2CC810
1:10 Clock Fanout Buffer
Features
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Low-voltage operation
V
DD
range from 2.5V to 3.3V
1:10 fanout
Over voltage tolerant input hot swappable
Drives either a 50-Ohm or 75-Ohm transmission line
Low-input capacitance
Low-output skew
Low-propagation delay
Typical (tpd < 4 ns)
High-speed operation > 500 MHz
Industrial versions available
Available packages include: SOIC, SSOP
Description
The Cypress series of network circuits are produced using
advanced 0.35-micron CMOS technology, achieving the
industries fastest logic and buffers.
The Cypress CY2CC810 fanout buffer features one input and
ten outputs. Designed for data communications clock
management applications, the large fanout from a single input
reduces loading on the input clock.
AVCMOS-type outputs dynamically adjust for variable
impedance matching and eliminate the need for series
damping resistors; they also reduce noise overall.
Block Diagram
Q1
Pin Configuration
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q 10
OUTPUT
(AVCMOS)
IN
GND
Q1
VDD
Q2
GND
Q3
VDD
Q4
GND
CY2CC810
VD D
IN
INPUT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
Q10
Q9
GND
Q8
VDD
Q7
GND
Q6
Q5
GND
20 pin SOIC/SSOP
Pin Description
Pin Number
1
2, 6, 10, 13, 17
4, 8, 15, 20
3, 5, 7, 9, 11, 12, 14, 16, 18, 19
Pin Name
IN
GND
Input
Ground
Power Supply
Output
Description
LVCMOS
Power
Power
AVCMOS
V
DD
Q1... Q10
Cypress Semiconductor Corporation
Document #: 38-07056 Rev. *C
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3901 North First Street
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San Jose
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CA 95134 鈥?408-943-2600
Revised December 14, 2002

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