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CY2CC1810OC Datasheet

  • CY2CC1810OC

  • 1:10 Clock Fanout Buffer with Output Enable

  • 8頁

  • CYPRESS

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COMLINK鈩?SERIES
CY2CC1810
1:10 Clock Fanout Buffer with Output Enable
Features
Low-voltage operation
V
DD
range from 2.5 to 3.3V
1:10 fanout
Drives either a 50-ohm or 75-ohm transmission line
Over voltage tolerant input hot swappable
Low input capacitance
Low output skew
Low propagation delay
Typical (tpd < 4 ns)
High-speed operation > 200 MHz
LVTTL-/LVCMOS-compatible input
鈥?Output disable to three-state
鈥?Industrial versions available
鈥?Packages available include: SOIC/SSOP
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Description
The Cypress series of network circuits is produced using
advanced 0.35-micron CMOS technology, achieving the
industries fastest logic and buffers.
The Cypress CY2CC1810 fanout buffer features one input and
ten three-state outputs.
Designed for data communications clock management appli-
cations, the large fanout from a single input reduces loading
on the input clock.
AVCMOS-type outputs dynamically adjust for variable
impedance-matching and eliminate the need for series-
damping resistors; they also reduce noise overall.
Block Diagram
Q1
OE#
Q2
Q3
Q4
Q5
IN
Q6
Q7
Q8
Q9
Q 10
OUTPUT
(AVCMOS)
Pin Configuration
VDD
GND
Q10
VDD
Q9
OE#
IN
GND
GND
Q8
VDD
Q7
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CY2CC1810
GND
Q1
VDD
Q2
GND
Q3
Q4
GND
Q5
VDD
Q6
GND
GND
24 pin SOIC/SSOP
Pin Description
Pin Number
1,7,8,12,13,17,20,24
3,10,15,22
5
6
2,4,9,11,14,16,18,19,21,23
Pin Name
G
ND
V
DD
OE#
IN
Q10........Q1
Ground
Power Supply
Output Enable
Input
Output
Pin Description
Power
Power
LVTTL/LVCMOS
LVTTL/LVCMOS
AVCMOS
Cypress Semiconductor Corporation
Document #: 38-07055 Rev. *C
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3901 North First Street
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San Jose
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CA 95134 鈥?408-943-2600
Revised December 14, 2002

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