Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY29FCT818T
SCCS012 - May 1994 - Revised February 2000
Diagnostic Scan Register
ter is designed for applications, such as diagnostics in sequen-
tial circuits, where it is desirable to load known data at a spe-
ci鏗乧 location in the circuit and to read the data at that location.
The shadow registers can load data from the output of the
FCT818T, and can be used as a right-shift register with
bit-serial input SDI and output SDO, using DCLK. The data
register input is multiplexed to enable loading from the shadow
register or from the data input pins using PCLK. Note that data
can be loaded simultaneously from the shadow register to the
pipeline register, and from the pipeline register to the shadow
register provided set-up and hold time requirements are
satis鏗乪d with respect to the two independent clock inputs.
In a typical application, the general-purpose register in the
FCT818T replaces an 8-bit data register in the normal data
path of a system. The shadow register is placed in an auxiliary
bit-serial loop which is used for diagnostics. During diagnostic
operation, data is shifted serially into the shadow register, then
transferred to the general purpose register to load a known
value into the data path. To read the contents at that point in
the data path, the data is transferred from the data register into
the shadow register, then shifted serially in the auxiliary
diagnostic loop to make it accessible to the diagnostics
controller. This data is then compared with the expected value
to diagnose faulty operation of the sequential circuit.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Features
鈥?/div>
Function, pinout and drive compatible with FCT, F Logic
and AM29818
鈥?/div>
FCT-C speed at 6.0 ns max. (Com鈥檒),
FCT-A speed at 12.0 ns max. (Mil)
鈥?/div>
Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
鈥?/div>
Edge-rate control circuitry for signi鏗乧antly improved
noise characteristics
鈥?/div>
Power-off disable feature
鈥?Matched rise and fall times
鈥?Fully compatible with TTL input and output logic levels
鈥?Sink current
64 mA (Com鈥檒),
20 mA (Mil)
Source current 32 mA (Com鈥檒),
3 mA (Mil)
鈥?/div>
8-Bit pipeline and shadow register
鈥?/div>
ESD > 2000V
Functional Description
The FCT818T contains a high-speed 8-bit general-purpose
data pipeline register and a high-speed 8-bit shadow register.
The general-purpose register can be used in an 8-bit wide
data path for a normal system application. The shadow regis-
Logic Block Diagram
Pin Configurations
LCC
Top View
D6
D5
D4
NC
D3
D2
D1
DIP, SOIC, QSOP
Top View
OE
DCLK
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
MODE
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
SDO
PCLK
SDI
DCLK
D
0
鈭扗
7
8-BIT
SHADOW
REGISTER
SDO
D
7
SDI
GND
NC
PCLK
SDO
Y
7
12
13
14
15
16
17
18
11 10 9 8 7 6 5
CLK
S
0
鈭扴
7
8
D
Q
19 2021 222324 25
Y6
Y5
MODE
4
3
2
1
28
27
26
D
0
DCLK
OE
NC
V
cc
MODE
Y
0
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
SDI
GND
MUX
8
8-BIT
PIPELINE
REGISTER
8
P
0
鈭扨
7
PCLK
OE
8
Y
0
鈭扽
7
Y4
NC
Y3
Y2
Y1
Copyright
漏
2000, Texas Instruments Incorporated
CY29FCT818CTSOCT 產品屬性
1
集成電路 (IC)
邏輯 - 移位寄存器
29FCT
管線寄存器
標準
1
8
通用
4.75 V ~ 5.25 V
-40°C ~ 85°C
表面貼裝
24-SOIC（0.295"，7.50mm 寬）
24-SOIC
Digi-Reel®
296-29772-6
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Single-PLL General-Purpose EPROM Programmable Clock Generato...
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2.5V or 3.3V, 200-MHz, 9-Output Clock Driver
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2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
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3.3V 125-MHz 8-Output Zero Delay Buffer
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Clocks and Buffers
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