CY29FCT52T
8-BIT REGISTERED TRANSCEIVER
SCCS010A 鈥?MAY 1994 鈥?REVISED OCTOBER 2001
D
D
D
D
D
D
D
D
Function, Pinout, and Drive Compatible
With FCT, F Logic, and AM2952
Reduced V
OH
(Typically = 3.3 V) Versions
of Equivalent FCT Functions
Edge-Rate Control Circuitry for
Significantly Improved Noise
Characteristics
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?200-V Machine Model (A115-A)
鈥?1000-V Charged-Device Model (C101)
I
off
Supports Partial-Power-Down Mode
Operation
Matched Rise and Fall Times
Fully Compatible With TTL Input and
Output Logic Levels
64-mA Output Sink Current
32-mA Output Source Current
Q OR SO PACKAGE
(TOP VIEW)
B
7
B
6
B
5
B
4
B
3
B
2
B
1
B
0
OEB
CPA
CEA
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
OEA
CPB
CEB
description
The CY29FCT52T has two 8-bit back-to-back registers that store data flowing in both directions between two
bidirectional buses. Separate clock, clock enable, and 3-state output-enable signals are provided for each
register. Both A outputs and B outputs are specified to sink 64 mA.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
PIN DESCRIPTION
NAME
A
B
CPA
CEA
OEA
CPB
CEB
OEB
A register inputs or B register outputs
B register inputs or A register outputs
Clock for the A register. When CEA is low, data enters the A register on the low-to-high transition of the CPA signal.
Clock enable for the A register. When CEA is low, data enters the A register on the low-to-high transition of the CPA signal. When CEA
is high, the A register holds its contents, regardless of CPA signal transitions.
Output enable for the A register. When OEA is low, the A register outputs are enabled onto the B lines. When OEA is high, the A outputs
are in the high-impedance state.
Clock for the B register. When CEB is low, data enters the B register on the low-to-high transition of the CPB signal.
Clock enable for the B register. When CEB is low, data enters the B register on the low-to-high transition of the CPB signal. When
CEB is high, the B register holds its contents, regardless of CPA signal transitions.
Output enable for the B register. When OEB is low, the B register outputs are enabled onto the A lines. When OEB is high, the B outputs
are in the high-impedance state.
DESCRIPTION
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
錚?/div>
2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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