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CY29949AIT Datasheet

  • CY29949AIT

  • 2.5V or 3.3V 200-MHz 1:15 Clock Distribution Buffer

  • 108.20KB

  • 7頁

  • CYPRESS

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CY29949
2.5V or 3.3V 200-MHz 1:15 Clock Distribution Buffer
Features
鈥?2.5V or 3.3V operation
鈥?200-MHz clock support
鈥?LVPECL or LVCMOS/LVTTL clock input
鈥?LVCMOS-/LVTTL-compatible outputs
鈥?15 clock outputs: drive up to 30 clock lines
鈥?1X and 1/2X configurable outputs
鈥?Output three-state control
鈥?350 ps max. output-to-output skew
鈥?Pin compatible with MPC949, MPC9449
鈥?Available in Commercial and Industrial temp. range
鈥?52-pin TQFP package
Description
The CY29949 is a low-voltage 200-MHz clock distribution
buffer with the capability to select either a differential LVPECL
or LVCMOS/LVTTL compatible input clocks. These clock
sources can be used to provide for test clocks as well as the
primary system clocks. All other control inputs are
LVCMOS/LVTTL compatible. The 15 outputs are LVCMOS or
LVTTL compatible and can drive 50鈩?series or parallel termi-
nated transmission lines. For series terminated transmission
lines, each output can drive one or two traces giving the device
an effective fanout of 1:30.
The CY29949 is capable of generating 1X and 1/2X signals
from a 1X source. These signals are generated and retimed
internally to ensure minimal skew between the 1X and 1/2X
signals. SEL(A:D) inputs allow flexibility in selecting the ratio
of 1X to1/2X outputs.
The CY29949 outputs can also be three-stated via the
MR/OE# input. When MR/OE# is set HIGH, it resets the
internal flip-flops and three-states the outputs.
Block Diagram
Pin Configuration
TCLK_SEL
NC
VDDC
QB2
VSS
QB1
VDDC
QB0
VSS
VSS
QA1
VDDC
QA0
VSS
0
1
0
1
R
1
2
PECL_CLK
PECL_CLK#
PECL_SEL
DSELA
0
1
2
52 51 50 49 48 47 46 45 44 43 42 41 40
QA(0:1)
1
R
2
0
1
3
QB(0:2)
DSELB
1
R
2
0
1
4
QC(0:3)
DSELC
1
R 2
0
1
6
QD(0:5)
MR/OE#
TCLK_SEL
VDD
TCLK0
TCLK1
PECL_CLK
PECL_CLK#
PCLK_SEL
DSELA
DSELB
DSELC
DSELD
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
CY29949
39
38
37
36
35
34
33
32
31
30
29
28
27
NC
VSS
QC0
VDDC
QC1
VSS
QC2
VDDC
QC3
VSS
VSS
QD5
NC
DSELD
MR/OE#
14 15 16 17 18 19 20 21 22 23 24 25 26
NC
VDDC
QD4
VSS
QD3
VDDC
QD2
VSS
QD1
VDDC
QD0
VSS
NC
Cypress Semiconductor Corporation
Document #: 38-07289 Rev. *D
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised November 6, 2003

CY29949AIT相關(guān)型號PDF文件下載

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    2.5V or 3.3V, 200-MHz, 9-Output Clock Driver
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  • 英文版
    2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    3.3V 125-MHz 8-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V 200-MHz 10-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
    CYPRESS
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
    CYPRESS [C...

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