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CY29948AIT Datasheet

  • CY29948AIT

  • 2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer

  • 7頁(yè)

  • CYPRESS

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48
CY29948
2.5V or 3.3V, 200-MHz, 1:12 Clock Distribution Buffer
Features
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2.5V or 3.3V operation
200-MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS-/LVTTL-compatible inputs
12 clock outputs: drive up to 24 clock lines
Synchronous Output Enable
Output three-state control
250 ps max. output-to-output skew
Pin compatible with MPC948, MPC948L, MPC9448
Available in Commercial and Industrial temp. range
32-pin TQFP package
Description
The CY29948 is a low-voltage 200-MHz clock distribution buff-
er with the capability to select either a differential LVPECL or
a LVCMOS/LVTTL compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are LVC-
MOS/LVTTL compatible. The 12 outputs are LVCMOS or LVT-
TL compatible and can drive 50鈩?series or parallel terminated
transmission lines. For series terminated transmission lines,
each output can drive one or two traces giving the device an
effective fanout of 1:24. The outputs can also be three-stated
via the three-state input TS#. Low output-to-output skews
make the CY29948 an ideal clock distribution buffer for nested
clock trees in the most demanding of synchronous systems.
The CY29948 also provides a synchronous output enable in-
put for enabling or disabling the output clocks. Since this input
is internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
Block Diagram
VDD
PECL_CLK
PECL_CLK#
TCLK
TCLK_SEL
SYNC_OE
TS#
0
1
VDDC
Pin Configuration
Q0
VDDC
VDDC
26
VSS
VSS
Q2
28
27
Q1
Q3
25
24
23
22
21
20
19
18
17
32
31
30
12
Q0-Q11
TCLK_SEL
TCLK
PECL_CLK
PECL_CLK#
SYNC_OE
TS#
VDD
VSS
1
2
3
4
5
6
7
8
29
CY29948
10
11
12
13
14
15
16
9
VSS
Q4
VDDC
Q5
VSS
Q6
VDDC
Q7
Q11
VDDC
Q10
VSS
Q9
VDDC
Cypress Semiconductor Corporation
Document #: 38-07288 Rev. *B
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3901 North First Street
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San Jose
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CA 95134 鈥?408-943-2600
Revised December 22, 2002
VSS
Q8

CY29948AIT相關(guān)型號(hào)PDF文件下載

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  • 英文版
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    Single-PLL General-Purpose EPROM Programmable Clock Generato...
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  • 英文版
    Single-PLL General-Purpose EPROM Programmable Clock Generato...
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 9-Output Clock Driver
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    3.3V 125-MHz 8-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V 200-MHz 10-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
    CYPRESS
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
    CYPRESS [C...

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