鈥?/div>
200-MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS/LVTTL compatible inputs
18 clock outputs: drive up to 36 clock lines
150 ps max. output-to-output skew
Dual or single supply operation:
鈥?3.3V core and 3.3V outputs
鈥?3.3V core and 2.5V outputs
鈥?2.5V core and 2.5V outputs
鈥?Pin compatible with MPC940L, MPC9109
鈥?Available in Commercial and Industrial temperature
鈥?32-pin LQFP package
Description
The CY29940 is a low-voltage 200-MHz clock distribution buff-
er with the capability to select either a differential LVPECL or
a LVCMOS/LVTTL compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are LVC-
MOS/LVTTL compatible. The eighteen outputs are 2.5V or
3.3V LVCMOS/LVTTL compatible and can drive 50鈩?series or
parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:36. Low out-
put-to-output skews make the CY29940 an ideal clock distri-
bution buffer for nested clock trees in the most demanding of
synchronous systems.
Block Diagram
Pin Configuration
VDD
PECL_CLK
PECL_CLK#
TCLK
TCLK_SEL
0
1
VDDC
32
31
30
29
28
27
26
25
VSS
VSS
TCLK
TCLK_SEL
PECL_CLK
PECL_CLK#
VDD
VDDC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
18
Q0-Q17
Cypress Semiconductor Corporation
Document #: 38-07283 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
Q17
Q16
Q15
VSS
Q14
Q13
Q12
VDDC
9
10
11
12
13
14
15
16
Q0
Q1
Q2
VDDC
Q3
Q4
Q5
VSS
CY29940
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 21, 2002
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