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CY29352AIT Datasheet

  • CY29352AIT

  • 2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer

  • 8頁

  • CYPRESS

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CY29352
2.5V or 3.3V, 200-MHz, 11-Output
Zero Delay Buffer
Features
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Output frequency range: 16.67 MHz to 200 MHz
Input frequency range: 16.67 MHz to 200 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
鹵2% max Output duty cycle variation
11 Clock outputs: Drive up to 22 clock lines
LVCMOS reference clock input
125-ps max output-output skew
PLL bypass mode
Spread Aware錚?/div>
Output enable/disable
Pin compatible with MPC9352 and MPC952
Industrial temperature range: 鈥?0擄C to +85擄C
32-Pin 1.0mm TQFP package
Description
The CY29352 is a low voltage high performance 200-MHz
PLL-based zero delay buffer designed for high speed clock
distribution applications.
The CY29352 features an LVCMOS reference clock input and
provides 11 outputs partitioned in 3 banks of 5, 4, and 2
outputs. Bank A divides the VCO output by 4 or 6 while Bank
B divides by 4 and 2 and Bank C divides by 2 and 4 per
SEL(A:C) settings, see
Function Table.
These dividers allow
output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3.
Each LVCMOS compatible output can drive 50鈩?series or
parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:22.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 16.67 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO is running at multiples of
the input reference clock set by the feedback divider, see
Table 1.
When PLL_EN# is HIGH, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
PLL_EN#
REFCLK
FB_IN
LPF
梅4 /
梅6
Pin Configuration
Phase
Detector
VCO
200-500MHz
梅2
QA0
QA1
QA2
QA3
QA4
VCO_SEL
SELC
SELB
SELA
MR/OE#
REFCLK
AVSS
FB_IN
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDDQC
QC1
QC0
VSS
VSS
QB3
QB2
VDDQB
VCO_SEL
SELA
梅4 /
梅2
CY29352
QB0
QB1
VSS
QB1
QB0
VDDQB
VDDQA
QA4
QA3
VSS
QB2
QB3
梅2 /
梅4
QC0
QC1
SELC
MR/OE#
Cypress Semiconductor Corporation
Document #: 38-07476 Rev. **
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3901 North First Street
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San Jose
,
CA 95134
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408-943-2600
Revised March 19, 2003
PLL_EN#
AVDD
VDD
QA0
VSS
QA1
QA2
VDDQA
9
10
11
12
13
14
15
16
SELB

CY29352AIT相關(guān)型號PDF文件下載

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    2.5V or 3.3V, 200-MHz, 9-Output Clock Driver
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  • 英文版
    2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
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  • 英文版
    2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    3.3V 125-MHz 8-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V 200-MHz 10-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
    CYPRESS
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
    CYPRESS [C...

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