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CY29351AIT Datasheet

  • CY29351AIT

  • 2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer

  • 288.38KB

  • 8頁

  • CYPRESS

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CY29351
2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
Features
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Output frequency range: 25 MHz to 200 MHz
Input frequency range: 25 MHz to 200 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
鹵2.5% max Output duty cycle variation
9 Clock outputs: Drive up to 18 clock lines
Two reference clock inputs: LVPECL or LVCMOS
150-ps max output-output skew
Phase-locked loop (PLL) bypass mode
Spread Aware鈩?/div>
Output enable/disable
Pin-compatible with MPC9351
Industrial temperature range: 鈥?0擄C to +85擄C
32-Pin 1.0-mm TQFP package
Functional Description
The CY29351 is a low voltage high performance 200 MHz
PLL-based zero delay buffer designed for high speed clock
distribution applications.
The CY29351 features LVPECL and LVCMOS reference clock
inputs and provides 9 outputs partitioned in 4 banks of 1, 1, 2,
and 5 outputs. Bank A divides the VCO output by 2 or 4 while
the other banks divide by 4 or 8 per SEL(A:D) settings, see
Functional Table.
These dividers allow output to input ratios of
4:1, 2:1, 1:1, 1:2, and 1:4. Each LVCMOS compatible output
can drive 50鈩?series or parallel terminated transmission lines.
For series terminated transmission lines, each output can
drive one or two traces giving the device an effective fanout of
1:18.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 25 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO is running at multiples of
the input reference clock set by the feedback divider, see the
Table 1.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
Pin Configuration
REF_SEL
SELA
PLL_EN
PLL_EN
VDDQB
27
TCLK
VSS
REF_SEL
TCLK
VCO
200 -
500 MHz
32
31
30
29
28
26
PECL_CLK
Phase
Detector
梅2 / 梅4
QA
25
VSS
QA
QB
LPF
梅4 / 梅8
QB
FB_IN
SELB
SELC
OE#
A VD D
FB_IN
SELA
SELB
SELC
SELD
A VSS
PE CL_C LK
1
2
3
4
5
6
7
8
C Y29351
24
23
22
21
20
19
18
17
QC0
VD D Q C
QC1
VS S
QD0
VD D Q D
QD1
VS S
10
11
12
13
14
QD3
15
VDDQD
梅4 / 梅8
QC1
VDD
QD4
VSS
OE#
PECL_CLK#
QD2
梅4 / 梅8
SELD
QD0
QD1
QD2
QD3
QD4
Cypress Semiconductor Corporation
Document #: 38-07475 Rev. *A
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3901 North First Street
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San Jose
,
CA 95134
16
QC0
9
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408-943-2600
Revised July 26, 2004

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  • 英文版
    2.5V or 3.3V, 200-MHz, 9-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    3.3V 125-MHz 8-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V 200-MHz 10-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer
    CYPRESS
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
    CYPRESS
  • 英文版
    2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
    CYPRESS [C...

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