錚?/div>
CPU
鈥?200-MHz differential CPU clock pairs
鈥?100-MHz differential SRC clocks
鈥?48-MHz USB clock
鈥?33-MHz PCI clock
鈥?66-MHz HyperTransport錚?clock
鈥?I
2
C support with readback capabilities
鈥?Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
鈥?3.3V power supply
鈥?56-pin SSOP and TSSOP packages
CPU
x2
SRC
x8
HTT66
x1
PCI
x1
REF
x3
USB_48
x1
Block Diagram
XIN
XOUT
CPU_STP#
CLKREQ[0:1]#
Pin Configuration
VDD_REF
REF[0:2]
VDD_CPU
CPUT[0:1], CPUC[0:1],
VDD_SRC
SRCT[0:5],SRCC[0:5]
VDD_SRCS
SRCST[0:1],SRCSC[0:1]
VDD_PCI
PCI
VDD_HTT
HTT66
XTAL
OSC
PLL1
PLL Ref Freq
Divider
Network
IREF
PD
VDD_48 MHz
PLL2
USB_48
SDATA
SCLK
I
2
C
Logic
XIN
XOUT
VDD_48
USB_48
VSS_48
NC
SCLK
SDATA
NC
CLKREQ#0
CLKREQ#1
SRCT5
SRCC5
VDD_SRC
VSS_SRC
SRCT4
SRCC4
SRCT3
SRCC3
VSS_SRC
VDD_SRC
SRCT2
SRCC2
SRCT1
SRCC1
VSS_SRC
SRCST1
SRCSC1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_REF
VSS_REF
REF0
REF1
REF2
VDD_PCI
PCI0
VSS_PCI
VDD_HTT
HTT66
VSS_HTT
CPUT0
CPUC0
VDD_CPU
VSS_CPU
CPUT1
CPUC1
VDDA
VSSA
IREF
VSS_SRC1
VDD_SRC1
SRCT0
SRCC0
VDD_SRCS
VSS_SRCS
SRCST0
SRCSC0
56 SSOP/TSSOP
Cypress Semiconductor Corporation
Document #: 38-07638 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised February 21, 2005
CY28RS480
next