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CY28409ZCT Datasheet

  • CY28409ZCT

  • Clock Synthesizer with Differential SRC and CPU Outputs

  • 18頁

  • CYPRESS

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CY28409
Clock Synthesizer with Differential SRC and CPU Outputs
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Supports Intel
錚?/div>
Pentium
錚?/div>
4-type CPUs
Selectable CPU frequencies
3.3V power supply
Ten copies of PCI clocks
Five copies of 3V66 with one optional VCH
Two copies 48-MHz USB clocks
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Three differential CPU clock pairs
One differential SRC clock
I
2
C support with readback capabilities
Ideal Lexmark Spread Spectrum profile for maximum
EMI reduction
鈥?56-pin SSOP and TSSOP packages
CPU
x3
SRC
x1
3V66
x5
PCI
x 10
REF
x2
48M
x2
Block Diagram
XIN
XOUT
CPU_STP#
PCI_STP#
FS_[A:B]
VTT_PWRGD#
IREF
VDD_3V66
3V66_[0:3]
Pin Configuration
VDD_REF
REF0:1
[1]
XTAL
OSC
PLL1
~
PLL Ref Freq
Divider
Network
VDD_CPU
CPUT[0:2], CPUC[0:2]
VDD_SRC
SRCT, SRCC
PLL2
2
VDD_PCI
PCIF[0:2]
PCI[0:6]
3V66_4/VCH
VDD_48MHz
DOT_48
USB_48
PD#
SDATA
SCLK
I
2
C
Logic
REF_0
REF_1
VDD_REF
XIN
XOUT
VSS_REF
PCIF0
PCIF1
PCIF2
VDD_PCI
VSS_PCI
PCI0
PCI1
PCI2
PCI3
VDD_PCI
VSS_PCI
PCI4
PCI5
PCI6
PD#
3V66_0
3V66_1
VDD_3V66
VSS_3V66
3V66_2
3V66_3
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
FS_B
VDD_A
VSS_A
VSS_IREF
IREF
FS_A
CPU_STP#
PCI_STP#
VDD_CPU
CPUT2
CPUC2
VSS_CPU
CPUT1
CPUC1
VDD_CPU
CPUT0
CPUC0
VSS_SRC
SRCT
SRCC
VDD_SRC
VTT_PWRGD#
VDD_48
VSS_48
DOT_48
USB_48
SDATA
3V66_4/VCH
56 SSOP/TSSOP
CY28409
Note:
1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.
Cypress Semiconductor Corporation
Document #: 38-07445 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised August 26, 2003

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