CY28404
CK409-Compliant Clock Synthesizer
Features
鈥?Supports Intel Springdale/Prescott (CK409)
鈥?Selectable CPU frequencies
鈥?3.3V power supply
鈥?Nine copies of PCI clock
鈥?Four copies 3V66 clock with optional VCH
鈥?Three copies 48-MHz clock
鈥?Three copies REF clock
錚?/div>
鈥?Two differential CPU clock pairs
鈥?Support SMBus/I
2
C Byte, Word, and Block Read/Write
鈥?Dial-A-Frequency
錚?/div>
鈥?Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
鈥?48-pin SSOP package
Table 1. Frequency Table
CPU
x2
3V66
x4
PCI
x9
REF
x3
48M
x3
Block Diagram
XIN
XOUT
Pin Configuration
VDD_REF
REF(0:2)
XTAL
OSC
PLL 1
PLL Ref Freq
Divider
Network
FS_(A:E)
VTT_PWRGD#
IREF
SEL24#
SELVCH
PLL2
2
MODE
PD#
**FS_A/REF_0
**FS_B/REF_1
VDD_REF
VDD_CPU
XIN
CPUT(0:1), CPUC(0:1)
XOUT
VSS_REF
*FS_C/PCIF0
*FS_D/PCIF1
*FS_E/PCIF2
VDD_PCI
VSS_PCI
VDD_3V66
PCI0
3V66_(0:2)
PCI1
PCI2
VDD_PCI
PCI3
PCIF(0:2)
VDD_PCI
VSS_PCI
PCI(0:5)
PCI4
PCI5
RESET#/PD#
3V66_3/VCH
*SEL24#/24_48MHz
DOT_48
USB_48
VDD_48MHz
VSS_48
DOT_48
USB_48
24_48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF_2
VDDA
VSSA
IREF
VSS_CPU
CPUT1
CPUC1
VDD_CPU
CPUT0
CPUC0
VSS
DNC***
DNC***
VDD
VTT_PWRGD#
SDATA*
SCLK*
3V66_0
3V66_1
VSS_3V66
VDD_3V66
3V66_2/MODE*
3V66_3/VCH/SELVCH**
VDD_48
~
2
SSOP-48
* 150k Internal Pull-up
** 150k Internal Pull-down
*** Do Not Connect
CY28404
SDATA
SCLK
I
2
C
Logic
WD
Timer
RESET#
Cypress Semiconductor Corporation
Document #: 38-07510 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised June 16, 2004
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