鈥?/div>
Synthesizer/Driver specifications
System frequency synthesizer for Intel Brookdale 845
and Brookdale 鈥?G Pentium 4
廬
chipsets
Programmable clock output frequency with less than
1-MHz increment
Integrated fail-safe Watchdog timer for system
recovery
Automatically switch to HW selected or SW
programmed clock frequency when Watchdog timer
time-out
Programmable 3V66 and PCI output frequency mode
鈥?Capable of generating system RESET after a Watchdog
timer time-out or a change in output frequency via
SMBus interface occurs
鈥?Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
鈥?Vendor ID and Revision ID support
鈥?Programmable drive strength support
鈥?Programmable output skew support
鈥?Power management control inputs
鈥?Available in 48-pin SSOP
Table 1. Frequency Table
CPU
x3
3V66
x4
PCI
x 10
REF
x2
48M
x1
24_48M
x1
Block Diagram
X1
X2
Pin Configuration
[1]
VDD_REF
REF0:1
XTAL
OSC
PLL 1
PLL Ref Freq
Divider
Network
VDD_CPU
*MULTSEL1/REF1
CPUT[0:1], CPUC[0:1],
VDD_REF
CPU_ITP, CPU_ITP#
*FS0:4
VTT_PWRGD#
*MULTSEL0:1
PLL2
Fract.
Aligner
VDD_3V66
3V66_0:2
VDD_PCI
PCI_F0:2
2
PCI0:6
VDD_48MHz
3V66_3/48MHz_1
VDD_48MHz
48MHz_0
PWRDWN#
24_48MHz
2
SDATA
SCLK
SMBus
Logic
X1
X2
GND_PCI
*FS2/PCI_F0
*FS3/PCI_F1
PCI_F2
VDD_PCI
*FS4/PCI0
PCI1
PCI2
GND_PCI
PCI3
PCI4
PCI5
PCI6
VDD_PCI
VTT_PWRGD#
RESET#
GND_48MHz
*FS0/48MHz_0
*FS1/24_48MHz
VDD_48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0/MULTSEL0**
GND_REF
VDD_CPU
CPU_ITP
CPU_ITP#
GND_CPU
PWRDWN#*
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
GNDC_CPU
IREF
VDD_CORE
GND_CORE
VDD_3V66
3V66_0
3V66_1
GND_3V66
3V66_2
3V66_3/48MHz_1
SCLK
SDATA
~
CY28378
RESET#
SSOP-48
Note:
1. Signals marked with 鈥?鈥?and 鈥?*鈥?have internal pull-up and pull-down resistors, respectively.
Cypress Semiconductor Corporation
Document #: 38-07519 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised February 28,2003
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