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CY28351OC Datasheet

  • CY28351OC

  • Differential Clock Buffer/Driver DDR400- and DDR333-Complian...

  • 8頁(yè)

  • CYPRESS

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CY28351
Differential Clock Buffer/Driver
DDR400- and DDR333-Compliant
Features
鈥?Supports 333-MHz and 400-MHz DDR SDRAM
鈥?60- 鈥?200-MHz operating frequency
鈥?Phase-locked loop (PLL) clock distribution for double
data rate synchronous DRAM applications
鈥?Distributes one clock input to ten differential outputs
鈥?External feedback pin (FBIN) is used to synchronize the
outputs to the clock input
鈥?Conforms to the DDRI specification
鈥?Spread Aware for electromagnetic interference (EMI)
reduction
鈥?48-pin SSOP package
Description
This PLL clock buffer is designed for 2.5-V
DD
and 2.5-AV
DD
operation and differential outputs levels.
This device is a zero delay buffer that distributes a clock input
(CLKIN) to ten differential pairs of clock outputs (YT[0:9],
YC[0:9]) and one feedback clock output (FBOUT). The clock
outputs are individually controlled by the serial inputs SCLK
and SDATA.
The two-line serial bus can set each output clock pair (YT[0:9],
YC[0:9]) to the Hi-Z state. When AV
DD
is grounded, the PLL is
turned off and bypassed for the test purposes.
The PLL in this device uses the input clock (CLKIN) and the
feedback clock (FBIN) to provide high-performance, low-skew,
low-jitter output differential clocks.
Block Diagram
10
Pin Configuration
YT0
YC0
YT1
YC1
YT2
YC2
SCLK
SDATA
YT4
YC4
YT5
YC5
YT6
YC6
CLKIN
PLL
FBIN
YT7
YC7
YT8
YC8
YT9
YC9
CY28351
Serial
Interface
Logic
YT3
YC3
AVDD
FBOUT
VSS
YC0
YT0
VDDQ
YT1
YC1
VSS
VSS
YC2
YT2
VDD
SCLK
CLKIN
NC
VDDI
AVDD
AVSS
VSS
YC3
YT3
VDDQ
YT4
YC4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VSS
YC5
YT5
VDDQ
YT6
YC6
VSS
VSS
YC7
YT7
VDDQ
SDATA
NC
FBIN
VDDQ
FBOUT
NC
VSS
YC8
YT8
VDDQ
YT9
YC9
VSS
Cypress Semiconductor Corporation
Document #: 38-07370 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised May 23, 2003

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