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CY28347ZCT Datasheet

  • CY28347ZCT

  • Universal Single-chip Clock Solution for VIA P4M266/KM266 DD...

  • 189.83KB

  • 22頁

  • CYPRESS

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CY28347
Universal Single-chip Clock Solution
for VIA P4M266/KM266 DDR Systems
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Supports VIA P4M266/KM266 chipsets
Supports Pentium
廬
4, Athlon錚?processors
Supports two DDR DIMMS
Provides
鈥?Two different programmable CPU clock pairs
鈥?Six differential DDR SDRAM pairs
鈥?Two low-skew/low-jitter AGP clocks
鈥?Six low-skew/low-jitter PCI clocks
鈥?One 48M output for USB
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?One programmable 24M or 48M for SIO
Dial-a-Frequency錚?and Dial-a-dB錚?features
Spread Spectrum for best electromagnetic interference
(EMI) reduction
SMBus-compatible for programmability
56-pin SSOP and TSSOP packages
Table 1. Frequency Selection Table
FS(3:0)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CPU
66.80
100.20
120.00
133.33
72.00
105.00
160.00
140.00
77.00
110.00
180.00
150.00
90.00
100.00
200.00
133.33
AGP
66.80
66.80
60.00
66.67
72.00
70.00
64.00
70.00
77.00
73.33
60.00
60.00
60.00
66.67
66.67
66.67
PCI
33.40
33.40
30.00
33.33
36.00
35.00
32.00
35.00
38.50
36.67
30.00
30.00
30.00
33.33
33.33
33.33
Block Diagram
XIN
XOUT
VDDR
XTAL
REF0
VDDI
SELP4_K7#
VDDC
CPUT/CPU0D_T
CPUC/CPU0D_C
VDDPCI
FS3 FS1
PCI(3:5)
PCI_F
MULTSEL
PCI2
PCI1
VDDAGP
AGP(0:1)
REF(0:1)
CPUCS_T
CPUCS_C
Pin Configuration
[1]
*FS0/REF0
VSSR
XIN
XOUT
VDDAGP
*MODE/AGP0
*SELP4_K7#/AGP1
*PCI_STP#
VSSAGP
**FS1/PCI_F
PCI1
*MULTSEL/PCI2
VSSPCI
PCI3
PCI4
VDDPCI
PCI5
*CPU_STP#
VSS48M
**FS3/48M
**FS2/24_48M
VDD48M
VDD
VSS
IREF
*PD#
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VTTPWRGD#/REF1
VDDR
VSSC
CPUT/CPUOD_T
CPUC/CPUOD_C
VDDC
VDDI
CPUCS_C
CPUCS_T
VSSI
FBOUT
BUF_IN
DDRT0
DDRC0
DDRT1
DDRC1
VDDD
VSSD
DDRT2
DDRC2
DDRT3
DDRC3
VDDD
VSSD
DDRT4
DDRC4
DDRT5
DDRC5
FS0
PCI_STP#
CPU_STP#
PD#
PLL1
FS2
CY28347
SDATA
SCLK
SMBus
PLL2
/2
VDD48M
48M
24_48M
SELSDR_DDR#
S2D
CONVERT
VDDD
FBOUT
DDRT(0:5)
DDRC(0:5)
BUF_IN
Note:
1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.
Cypress Semiconductor Corporation
Document #: 38-07352 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised December 26, 2002

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