音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

CY28346ZCT Datasheet

  • CY28346ZCT

  • Clock Synthesizer with Differential CPU Outputs

  • 20頁

  • CYPRESS

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

CY28346
Clock Synthesizer with Differential CPU Outputs
Features
鈥?Compliant with Intel廬 CK 408 Mobile Clock Synthesizer
specifications
鈥?3.3V power supply
鈥?Three differential CPU clocks
鈥?Ten copies of PCI clocks
Table 1. Frequency Table
[1]
S2
1
1
1
1
0
0
0
0
M
M
S1
0
0
1
1
0
0
1
1
0
0
S0
0
1
0
1
0
1
0
1
0
1
CPU (0:2)
66M
100M
200M
133M
66M
100M
200M
133M
Hi-Z
TCLK/2
3V66
66M
66M
66M
66M
66M
66M
66M
66M
Hi-Z
TCLK/4
66BUFF(0:2)/
3V66(0:4)
66IN
66IN
66IN
66IN
66M
66M
66M
66M
Hi-Z
TCLK/4
66IN/3V66鈥?
66-MHz clock input
66-MHz clock input
66-MHz clock input
66-MHZ clock input
66M
66M
66M
66M
Hi-Z
TCLK/4
PCI_FPCI
66IN/2
66IN/2
66IN/2
66IN/2
33 M
33 M
33 M
33 M
Hi-Z
TCLK/8
REF
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
Hi-Z
TCLK
USB/ DOT
48M
48M
48M
48M
48M
48M
48M
48M
Hi-Z
TCLK/2
鈥?5/6 copies of 3V66 clocks
鈥?SMBus support with read-back capabilities
鈥?Spread Spectrum electromagnetic interference (EMI)
reduction
鈥?Dial-a-Frequency鈩?features
鈥?Dial-a-dB鈩?features
鈥?56-pin TSSOP and SSOP packages
Block Diagram
XIN
XOUT
PLL1
CPU_STP#
IREF
VSSIREF
S(0:2)
MULT0
VTT_PG#
PCI_STP#
PLL2
/2
Pin Configuration
REF
VDD
XIN
XOUT
VSS
PCIF0
PCIF1
PCIF2
VDD
VSS
PCI0
PCI1
PCI2
PCI3
VDD
VSS
PCI4
PCI5
PCI6
VDD
VSS
66B0/3V66_2
66B1/3V66_3
66B2/3V66_4
66IN/3V66_5
PD#
VDDA
VSSA
VTT_PG#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF
S1
S0
CPU_STP#
CPUT0
CPUC0
VDD
CPUT1
CPUC1
VSS
VDD
CPUT2
CPUC2
MULT0
IREF
VSSIREF
S2
48MUSB
48MDOT
VDD
VSS
3V66_1/VCH
PCI_STP#
3V66_0
VDD
VSS
SCLK
SDATA
CPUT(0:2)
CPUC(0:2)
3V66_0
3V66_1/VCH
PCI(0:6)
PCI_F(0:2)
48M USB
48M DOT
CY28346
PD#
SDATA
SCLK
VDDA
WD
Logic
I2C
Logic
66B[0:2]/3V66[2:4]
Power
Up Logic
66IN/3V66-5
Note:
1. TCLK is a test clock driven on the XTAL_IN input during test mode. M= driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a
0 state will be latched into the device鈥檚 internal state register.
Cypress Semiconductor Corporation
Document #: 38-07331 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 26, 2002

CY28346ZCT 產(chǎn)品屬性

  • 2,000

  • 集成電路 (IC)

  • 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器

  • *

CY28346ZCT相關(guān)型號PDF文件下載

  • 型號
    版本
    描述
    廠商
    下載
  • 英文版
    Intel CK408 Mobile Clock Synthesizer
    CYPRESS
  • 英文版
    Intel CK408 Mobile Clock Synthesizer
    CYPRESS [C...
  • 英文版
    Spread Spectrum Timing Solution for Serverworks Chipset
    CYPRESS
  • 英文版
    Spread Spectrum Timing Solution for Serverworks Chipset
    CYPRESS [C...
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    Clock Generator for Serverworks Grand Champion Chipset Appli...
    CYPRESS
  • 英文版
    Frequency Generator for Intel Integrated Chipset
    CYPRESS
  • 英文版
    Frequency Generator for Intel Integrated Chipset
    CYPRESS [C...
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    FTG for VIA PL133T and PLE133T
    CYPRESS
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    Clocks and Buffers
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    Clocks and Buffers
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    FTG for Intel? Pentium? 4 CPU and Chipsets
    CYPRESS
  • 英文版
    FTG for Intel Pentium 4 CPU and Chipsets
    CYPRESS
  • 英文版
    FTG for Intel Pentium 4 CPU and Chipsets
    CYPRESS [C...
  • 英文版
    FTG for VIA PT880 Serial Chipset
    CYPRESS
  • 英文版
    FTG for VIA PT880 Serial Chipset
    CYPRESS [C...

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！