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CY28342ZC Datasheet

  • CY28342ZC

  • High-performance SiS645/650 Pentium 4 Clock Synthesizer

  • 22頁

  • CYPRESS

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42
CY28342
High-performance SiS645/650 Pentium
錚?/div>
4 Clock Synthesizer
Features
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Supports Pentium
錚?/div>
4-type CPUs
3.3V power supply
Eight copies of PCI clocks
One 4-MHz USB clock
Two copies of ZCLK clocks
One 48-MHz/24-MHz programmable SIO clock
Two differential CPU clock pairs
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
SMBus support with read-back capabilities
Spread Spectrum EMI reduction
Dial-a-Frequency
廬
features
Dial-a-Ratio鈩?features
Dial-a-dB
廬
features
48-pin SSOP and TSSOP packages
Watchdog Function
Block Diagram
XIN
XOUT
PLL1
CPU_STP#
IREF
FS(0:4)
MULT0
VTTPWRGD
PCI_STP#
PLL2
Power
on
Latch
/2
Pin Configuration
[1]
REF(0:2)
CPU(0:1)T
CPU(0:1)C
SDCLK
AGP(0:1)
ZCLK(0:1)
PCI(0:5)
PCI_F(0:1)
48M
48M_24M#
PD#
SDATA
SCLK
WD
Logic
I2C
Logic
SRESET#
VDDR
**FS0/REF0
**FS1/REF1
**FS2/REF2
VSSR
XIN
XOUT
VSSZ
ZCLK0
ZCLK1
VDDZ
*SRESET#/PCI_STP#
VDDP
**FS3/PCI_F0
**FS4/PCI_F1
PCI0
PCI1
VSSP
VDDP
PCI2
PCI3
PCI4
PCI5
VSSP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDSD
SDCLK
VSSSD
CPU_STP#*
CPU1T
CPU1C
VDDC
VSSC
CPU0T
CPU0C
IREF
VSSA
VDDA
SCLK
SDATA
PD#/VTTPWRGD*
VSSAGP
AGP0
AGP1
VDDAGP
VDD48M
48M
24_48M/MULT0*
VSS48M
48 Pin SSOP andf TSSOP
Note:
1. Pins marked with [*] have internal pull-up resistors. Pins marked with [**] have internal pull-down resistors.
Cypress Semiconductor Corporation
Document #: 38-07349 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised July 29, 2002
&<

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