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CY28339ZCXT Datasheet

  • CY28339ZCXT

  • Intel CK408 Mobile Clock Synthesizer

  • 18頁

  • CYPRESS

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CY28339
Intel
錚?/div>
CK408 Mobile Clock Synthesizer
Features
鈥?Compliant with Intel
廬
CK 408 rev 1.1 Mobile Clock
Synthesizer specifications
鈥?3.3V power supply
鈥?Two differential CPU clocks
鈥?Nine copies of PCI clocks
鈥?Three copies configurable PCI free-running clocks
鈥?Two 48 MHz clocks (USB, DOT)
鈥?Five/six copies of 3V66 clocks
Table 1. Frequency Table
[1]
S2
1
1
0
0
M
S1
0
1
0
1
0
CPU (1:2)
100M
133M
100M
133M
TCLK/2
3V66
66M
66M
66M
66M
TCLK/4
66BUFF(0:2)/
3V66(0:4)
66IN
66IN
66M
66M
TCLK/4
66IN/3V66鈥?
66-MHz clock input
66-MHZ clock input
66M
66M
TCLK/4
PCIF, PCI
66IN/2
66IN/2
33 M
33 M
TCLK/8
REF
14.318M
14.318M
14.318M
14.318M
TCLK
USB/ DOT
48M
48M
48M
48M
TCLK/2
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
One VCH clock
One reference clock at 14.318 MHz
SMBus support with read-back capabilities
Ideal Lexmark profile Spread Spectrum electromag-
netic interference (EMI) reduction
鈥?Dial-a-Frequency鈩?features
鈥?Dial-a-dB鈩?features
鈥?48-pin TSSOP package
Block Diagram
X1
X2
Pin Configuration
VDD_REF
PWR
XTAL
OSC
REF
XIN
XOUT
GND_REF
VDD_CPU
CPUT1:2
CPUC1:2
VDD_PCI
PCIF
Stop
Clock
Control
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
VDD_REF
REF
S1
CPU_STOP#
VDD_CPU
CPUT1
CPUC1
GND_CPU
VDD_CPU
CPUT2
CPUC2
IREF
S2
USB_48MHz
DOT_48MHz
VDD_48 MHz
GND_48 MHz
3V66_1/VCH
PCI_STOP#
3V66_0
VDD_3V66
GND_3V66
SCLK
SDATA
PLL Ref Freq
PLL 1
S1:2
VTT_PWRGD##
CPU_STOP#
Gate
Divider
Network
PWR
Stop
Clock
Control
PCI7
PCI8
PCIF
GND_PCI
PCI0
PCI1
PCI2
VDD_PCI
PCI4
PCI5
PCI6
VDD_3V66
GND_3V66
66BUFF0/3V66_2
66BUFF1/3V66_3
66BUFF2/3V66_4
66IN/3V66_5
PD#
VDD_CORE
GND_CORE
VTT_PWRGD#
PWR
PCI0:2
PCI4:8
CY28339
PCI_STOP#
PD#
PWR
37
36
35
34
33
32
31
30
29
28
27
26
25
/2
VDD_3V66
3V66_0:1
PWR
3V66_2:4/
66BUFF0:2
3V66_5/ 66IN
PLL 2
VDD_48MHz
PWR
USB (48MHz)
DOT (48MHz)
VCH_CLK/ 3V66_1
SDATA
SCLK
SMBus
Logic
Note:
1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up,
a 0 state will be latched into the device鈥檚 internal state register.
Cypress Semiconductor Corporation
Document #: 38-07507 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised June 25, 2004

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