鈥?/div>
Programmable clock output frequency with less than
1 MHz increment
鈥?Integrated fail-safe Watchdog Timer for system
recovery
鈥?Automatic switch to HW-selected or SW-programmed
clock frequency when Watchdog Timer time-out occurs
鈥?System RESET generation capability after a Watchdog
Timer time-out occurs or a change in output frequency
via SMBus interface
鈥?Support SMBus byte Read/Write and block Read/ Write
operations to simplify system BIOS development
鈥?Vendor ID and Revision ID support
鈥?Programmable drive strength for SDRAM and PCI
output clocks
鈥?Programmable output skew for CPU, PCI and SDRAM
鈥?Maximized EMI Suppression using Cypress鈥檚 Spread
Spectrum technology
鈥?Available in 48-pin SSOP and TSSOP packages
Key Specifications
CPU to CPU Output Skew:.......................................... 175 ps
PCI to PCI Output Skew:............................................. 500 ps
Block Diagram
VDD_REF
REF0
X1
X2
XTAL
OSC
PLL Ref Freq
Pin Configuration
[1]
GND_CPU
*FS2/REF1
REF0
VTT_PWRGD#
REF1/FS2*
MULT_SEL
IREF
VTT_PWRGD#
PCI_STOP#
CPU_STOP#
PD#
PLL 1
梅2,3,4
CPU0:1, CPUT, CPUC
VDD_PCI
PCI0_F/FS4*
PCI1/FS3*
PCI2:6
SDATA
SCLK
SMBus
Logic
Reset
Logic
PLL2
梅2
RST#
VDD_48MHz
48MHz/FS0*
VDD_REF
GND_REF
X1
X2
VDD_PCI
*FS4/PCI0_F
*FS3/PCI1
GND_PCI
PCI2
PCI3
PCI4
PCI5
PCI6
SDRAMIN
*CPU_STOP#
*PCI_STOP#
*PD#
*MULT_SEL
GND_48MHz
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CPU0
CPU1
VDD_CPU_2.5
VDD_CPU_3.3
CPUT
CPUC
GND_CPU
RST#
IREF
SDRAM6
GND_SDRAM
SDRAM0
SDRAM1
VDD_SDRAM
SDRAM2
SDRAM3
GND_SDRAM
SDRAM4
SDRAM5
VDD_SDRAM
VDD_48MHz
48MHz/FS0*
24_48MHz/FS1*
SCLK
CY28317-2
SDRAMIN
7
24_48MHz/FS1*
VDD_SDRAM
SDRAM0:6
Note:
1. Signals marked with 鈥?鈥?have internal pull-up resistors.
Cypress Semiconductor Corporation
Document #: 38-07094 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 26, 2002
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