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CY28301 Datasheet

  • CY28301

  • Frequency Generator for Intel Integrated Chipset

  • 15頁(yè)

  • CYPRESS

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CY28301
Frequency Generator for Intel
廬
Integrated Chipset
Features
鈥?Single chip FTG solution for Intel
廬
Solano/810E/810
鈥?Support SMBus byte Read/Write and block Read/Write
operations to simplify system BIOS development
鈥?Vendor ID and revision ID support
鈥?Maximized EMI suppression using Cypress鈥檚 Spread
Spectrum technology
鈥?Low jitter and tightly controlled clock skew
鈥?Two copies of CPU clock
鈥?Thirteen copies of SDRAM clock
鈥?Eight copies of PCI clock
鈥?One copy of synchronous APIC clock
鈥?Three copies of 66-MHz outputs
鈥?Two copies of 48-MHz outputs
鈥?One copy of 14.31818-MHz reference clock
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: .............250 ps
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ................................................... 500 ps
CPU, 3V66 Output Skew:............................................ 175 ps
SDRAM, APIC, 48-MHz Output Skew: ........................250 ps
PCI Output Skew:........................................................ 500 ps
CPU to SDRAM Skew (@ 133 MHz) ......................... 鹵0.5 ns
CPU to SDRAM Skew (@ 100 MHz)..................4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz) ........................7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead)...........................1.5 to 3.5 ns
PCI to APIC Skew ...................................................... 鹵0.5 ns
Block Diagram
VDD_REF
Pin Configuration
[1]
X1
X2
XTAL
OSC
PLL REF FREQ
SDATA
SCLK
SMBus
Logic
Divider,
Delay, and
Phase
Control
Logic
(FS0:4)
PLL 1
PD#
PLL2
/2
VDD_REF
X1
X2
GND_REF
VDD_CPU
GND_3V66
3V66_0
CPU0:1
3V66_1
2
3V66_2
VDD_3V66
VDD_APIC
VDD_PCI
APIC
PCI0
PCI1
VDD_3V66
PCI2/SEL24_48MHz#*
3V66_0:2
GND_PCI
3
VDD_PCI
PCI3
PCI4
PCI0
PCI5
PCI1
VDD_PCI
PCI2/SEL24_48MHz#*
PCI6
PCI3:7
5
PCI7
GND_PCI
VDD_SDRAM
PD#*
SDRAM0:11,
SCLK
13
SDRAM_F
SDATA
VDD_SDRAM
SDRAM11
SDRAM10
VDD_48MHz
GND_SDRAM
REF/FS1
48MHz/FS0
24_48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF/FS1*
VDD_APIC
APIC
VDD_CPU
CPU0
CPU1
GND_CPU
GND_SDRAM
SDRAM0
SDRAM1
SDRAM2
VDD_SDRAM
SDRAM3
SDRAM4
SDRAM5
GND_SDRAM
SDRAM6
SDRAM7
SDRAM_F
VDD_SDRAM
GND_48MHz
24_48MHz
48MHz/FS0*
VDD_48MHz
VDD_SDRAM
SDRAM8
SDRAM9
GND_SDRAM
Note:
1. Internal 100K pull-up resistors present on inputs marked with *. Design
should not rely solely on internal pull-up resistor to set I/O pins HIGH.
CY28301
Cypress Semiconductor Corporation
Document #: 38-07011 Rev. *C
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised September 24, 2002

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