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CY27H512 Datasheet

  • CY27H512

  • 64K x 8 High-Speed CMOS EPROM

  • 11頁

  • CYPRESS

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PRELIMINARY
Features
D
D
D
D
D
D
D
D
CMOS for optimum speed/power
High speed
t
AA
= 25 ns max. (commercial)
t
AA
= 35 ns max. (military)
Low
power
275 mW max.
Less than 85 mW when deselected
Byte wide memory organization
100% reprogrammable in the
windowed package
EPROM technology
Capable of withstanding >2001V
static discharge
Available in
32 pin PLCC
28 pin TSOP I
28 pin, 600 mil plastic or
hermetic DIP
32 pin hermetic LCC
The CY27H512 is a high performance,
512K CMOS EPROM organized in 64
Kbytes. It is available in industry standard
28 pin, 600 mil DIP, 32 pin LCC and
PLCC, and 28 pin TSOP I packages.
These devices offer high density storage
combined with 40 MHz performance. The
CY27H512 is available in windowed and
opaque packages. Windowed packages al
low the device to be erased with UV light
for 100% reprogrammability.
The CY27H512 is equipped with a power
down chip enable (CE) input and output
enable (OE). When CE is deasserted, the
device powers down to a low power stand
by mode. The OE pin three states the out
puts without putting the device into stand
by mode. While CE offers lower power,
OE provides a more rapid transition to and
from three stated outputs.
Functional Description
64K x 8 High Speed CMOS
EPROM
The memory cells utilize proven EPROM
CY27H512
floating gate technology and byte wide in
telligent programming algorithms. The
EPROM cell requires only 12.75 V for the
supervoltage and low programming cur
rent allows for gang programming. The de
vice allows for each memory location to be
tested 100%, because each location is writ
ten to, erased, and repeatedly exercised
prior to encapsulation. Each device is also
tested for AC performance to guarantee
that the product will meet DC and AC
specification limits after customer pro
gramming.
The CY27H512 is read by asserting both
the CE and the OE inputs. The contents of
the memory location selected by the ad
dress on inputs A
15
-A
0
will appear at the
outputs O
7
-O
0
.
Logic Block Diagram
Pin Configurations
DIP
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
POWER DOWN
O
6
O
5
MULTIPLEXER
O
4
O
3
O
1
PROGRAMMABLE
ARRAY
O
2
O
0
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
ADDRESS
DECODER
A
1
A
0
O
0
O
1
O
2
GND
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
A
14
A
13
A
8
A
9
A
11
OE/V
PP
A
10
CE
O
7
O
6
O
5
O
4
O
3
LCC/PLCC
O
7
[1]
H512 2
Top View
A 15
V
CC
A 14
A 12
A 13
DU
A
15
4
A
6
A
5
A
4
A
3
A
2
CE
OUTPUT ENABLE
OE
DECODER
A
1
A
0
NC
O
0
H512 1
5
6
7
8
9
10
11
12
13
A7
3
2
1 32 31 30
29
28
27
26
25
24
23
22
21
A
8
A
9
A
11
NC
OE/V
PP
A
10
CE
O
7
O
6
14 15 16 17 1819 20
GND
DU
O
1
O
2
O
3
O
4
5
1. For LCC/PLCC only: Pins 1 and 17 are common and tied to the die at
tach pad. They should not be used.
Note:
Cypress Semiconductor Corporation
D
3901 North First Street
1
D
San Jose
D
CA 95134
O
H512 3
D
408-943-2600
November 1994

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