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CY27EE16ZE Datasheet

  • CY27EE16ZE

  • 1 PLL In-System Programmable Clock Generator with Individual...

  • 164.76KB

  • 17頁

  • CYPRESS

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CY27EE16ZE
1 PLL In-System Programmable Clock Generator
with Individual 16K EEPROM
Features
鈥?18 kbits of EEPROM
16 kbits independent scratch
2 kbits dedicated to clocking functions
Benefits
Higher level of integration and reduced component count by
combining EEPROM and PLL. Independent EEPROM may be used
for scratch memory, or to store up to eight clock configurations
鈥?Integrated, phase-locked loop with programmable P
High-performance PLL enables control of output frequencies that are
and Q counters, output dividers, and optional
customizable to support a wide range of applications
analog VCXO, digital VCXO, spread spectrum for
EMI reduction
鈥?In system programmable through I
2
C Serial
Programming Interface (SPI). Both the SRAM and
non-volatile EEPROM memory bits are program-
mable with the 3.3V supply
鈥?Low-jitter, high-accuracy outputs
鈥?VCXO with analog adjust
Familiar industry standard eases programming effort and enables
update of data stored in 16K EEPROM scratchpad and 2K EEPROM
clock control block while CY27EE16ZE is installed in system
Meets critical timing requirements in complex system designs
Write Protect (WP pin) can be programmed to serve as an analog
control voltage for a VCXO.The VCXO function is still available with
a DCXO, or digitally controlled (through SPI) crystal oscillator if the
pin is functioning as WP
Meets industry-standard voltage platforms
Industry standard packaging saves on board space
Input Frequency Range
Output Frequency Range
鈥?3.3V Operation (optional 2.5V outputs)
鈥?20-lead Exposed Pad, EP-TSSOP
Part Number
CY27EE16ZE
Outputs
6
1 鈥?167 MHz (Driven Clock Input) {Commercial} 80 kHz 鈥?200 MHz (3.3V) {Commercial}
1 鈥?50 MHz (Driven Clock Input) {Industrial}
80 kHz 鈥?67 MHz (3.3V) {Industrial}
8 鈥?30 MHz (Crystal Reference) {Comm. or Ind.} 80 kHz 鈥?67 MHz (2.5V) {Commercial}
80 kHz 鈥?150 MHz (2.5V) {Industrial}
Logic Block Diagram
XIN
XOUT
OSC
Q
桅
VCO
P
OUTPUT
DIVIDERS
Output
Crosspoint
Switch
Array
CLOCK1
CLOCK2
CLOCK3
CLOCK4
PLL
CLOCK5
VCX/WP
PDM/OE
Clock
Configuration
CLOCK6
8x2k EEPROM
Memory Array
Pin Configurations
CY27EE16ZE
[I
2
C- SPI:]
SCL
SDAT
20-pin EP-TSSOP
XIN 1
VDD 2
VDD
VSS
VDDL
VSSL
AVDD AVSS
20 XOUT
19 VDD
18 CLOCK5
17 VCXO/WP
16 VSS
15 CLOCK4
14 VDDL
13 SCL
12 CLOCK3
11 VDDL
CLOCK6 3
AVDD 4
SDAT 5
AVSS 6
VSSL 7
CLOCK1 8
CLOCK2 9
OE/PDM 10
Cypress Semiconductor Corporation
Document #: 38-07440 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised June 30, 2003

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