CY27C128 automatically powers down
into a low power stand by mode. The
D
Wide speed range
CY27C128 is packaged in the industry
45 ns to 200 ns (commercial and
standard 600 mil DIP and LCC packages.
military)
The CY27C128 is also available in a Cer
D
Low power
DIP package equipped with an erasure
window to provide for reprogrammability.
248 mW (commercial)
When exposed to UV light, the EPROM
303 mW (military)
is erased and can be reprogrammed. The
D
Low standby power
cells utilize
Less than 83 mW when deselected
memorygate technologyproven EPROM
floating
and byte wide in
D
鹵10% Power supply tolerance
telligent programming algorithms.
Functional Description
The CY27C128 offers the advantage of
performance
The CY27C128 is a high performance lower power and superior EPROM cell and
programming yield. The
re
16,384 word by 8 bit CMOS EPROM. quires only 12.5V for the super voltage,
When disabled (CE HIGH), the
Features
128K (16K x 8 Bit) CMOS EPROM
CY27C128
and low current requirements allow for
gang programming. The EPROM cells al
low each memory location to be tested
100% because each location is written
into, erased, and repeatedly exercised
prior to encapsulation. Each EPROM is
also tested for AC performance to guar
antee that after customer programming,
the product will meet both DC and AC
specification limits.
Reading the CY27C128 is accomplished
by placing active LOW signals on OE and
CE. The contents of the memory location
addressed by the address lines (A
0
- A
13
)
will become available on the output lines
(O
0
- O
7
).
Logic Block Diagram
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
COLUMN
A
2
A
1
A
0
ADDRESS
O
5
ROW
ADDRESS
128 x 1024
PROGRAMABLE
ARRAY
8 x 1 OF 128
MULTIPLEXER
O
7
O
6
V
PP
A
12
A
7
A
6
A
5
A
4
O
4
A
3
A
2
A
1
O
3
A
0
O
0
O
1
O
2
O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Configurations
DIP/Flatpack
28
27
26
25
24
27C128
23
22
21
20
19
18
17
16
15
V
CC
PGM
A
13
A
8
A
9
A
11
OE
A
10
CE
O
7
O
6
O
5
O
4
O
3
C128 2
O
1
POWER DOWN
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
O
0
5
6
7
8
9
10
11
12
13
27C128
LCC/PLCC
[1]
V
PP
V
CC
PGM
A 12
A7
4
3
2
1 32 31 30
29
28
27
26
25
24
23
22
21
A
8
A
9
A
11
NC
OE
A
10
CE
O
7
O
6
A 13
O
C128 3
5
DU
DU
ADDRESS
DECODER
14 15 16 17 1819 20
GND
1
2
3
O
4
O
O
O
0
CE
OE
C128 1
Selection Guide
27C128-45 27C128-55 27C128-70 27C128-90 27C128-120 27C128-150 27C128-200
Maximum Access Time (ns)
45
55
70
90
120
150
200
Maximum
45
45
45
45
45
45
45
Operating
[2]
Com'l
55
55
55
55
55
55
55
Mil
Current (mA)
15
15
15
15
15
15
15
Standby Current Com'l
(mA)
( A)
20
20
20
20
20
20
20
Mil
Chip Select Time (ns)
45
55
70
90
120
150
200
Output Enable Time (ns)
15
20
25
30
30
40
40
Notes:
1. For PLCC only: Pins 1 and 17 are common and tied to the die attach 2. Add 2 mA/MHz for AC power component.
pad. They must therefore be DU (don't use) for the PLCC package.
Cypress Semiconductor Corporation
D
3901 North First Street
1
D
San Jose
D
CA 95134
O
D
408-943-2600
February 1994
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