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CY26121ZC-11 Datasheet

  • CY26121ZC-11

  • PacketClock Spread Spectrum Clock Generator

  • 65.54KB

  • 6頁

  • CYPRESS

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CY26121
PacketClock鈩?Spread Spectrum Clock Generator
Features
鈥?Integrated phase-locked loop (PLL)
鈥?Low jitter, high-accuracy outputs
鈥?3.3V operation
鈥?25-MHz input frequency
鈥?66.66-MHz or 33.33-MHz selectable output frequency
(orig, -3,-11,-31)
鈥?33.33-MHz or 25-MHz selectable output frequency
(-2,-21)
Benefits
High-performance PLL tailored for Spread Spectrum appli-
cation
Meets critical timing requirements in complex system
designs
Enables application compatibility
Works with commonly available crystal or driven reference
Downspread Spread Spectrum with 30-kHz nominal
modulation frequency
Frequency Table for CLKA-D
Part Number
CY26121
CY26121-2
CY26121-3
CY26121-11
CY26121-21
CY26121-31
CLKSEL=0
66.66 MHz
33.33 MHz
66.66 MHz
66.66 MHz
33.33 MHz
66.66 MHz
CLKSEL=1
33.33
25.00
33.33
33.33
25.00
33.33
Spread%
鈥?.8%
鈥?.8%
鈥?.4%
鈥?.8%
鈥?.8%
鈥?.4%
Parallel Crystal Load
6 pF
6 pF
6 pF
15 pF
15 pF
15 pF
Logic Block Diagram
25 MHz XIN
XOUT
OSC.
VDDL
PLL
with
Modulation Control
CLKA
CLKB
CLKC
SSON
OUTPUT
MULTIPLEXER
AND
DIVIDERS
Flash Configuration
CLKD
VSSL
CLKSEL
REF
VDD
AVDD AVSS
VSS
Pin Configuration
CY26121
16-pin TSSOP
XIN
VDD
AVDD
CLKSEL
AVSS
VSSL
CLKA
CLKB
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XOUT
NC
REF
VSS
CLKD
VDDL
SSON
CLKC
Cypress Semiconductor Corporation
Document #: 38-07350 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised February 11, 2003

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