鈥?/div>
25- to 200-MHz operating frequency range
Wide range of spread selections (9)
Accepts clock or crystal inputs
Provides four clocks
鈥?SSCLK1a
鈥?SSCLK1b
鈥?SSCLK2
鈥?REFOUT
鈥?Low-power dissipation
鈥?3.3V = 70 mW (typical @ 40 MHz, no load)
鈥?Center spread modulation
鈥?Low cycle-to cycle jitter
鈥?16-pin SOIC package
Applications
鈥?High-resolution VGA controllers
鈥?LCD panels and monitors
鈥?Printers and MFPs
Benefits
鈥?Peak EMI reduction by 8 to 16 dB
鈥?Fast time to market
鈥?/div>
Cost reduction
Block Diagram
Pin Configuration
REFOFF
2
300K
3 REFOUT
Xin/
CLK
1
REFERENCE
DIVIDER
XIN/CLKIN
REFOFF
1
2
16
15
XOUT
SSCLK2
VSS
PD
CP
Loop
Filter
REFOUT
VDD
3
4
5
6
7
8
CY25566
14
13 S0
12 S1
11
VSS
Xout 16
VSS
MODULATION
CONTROL
FEEDBACK
DIVIDER
vco
S2
S3
SSCLK1a
10 SSCC
9
SSCLK1b
VDD 4
INPUT
DECODER
LOGIC
VDD
VDD
DIVIDER
&
MUX
8 SSCLK1a
9 SSCLK1b
/2
15 SSCLK2
VSS 5
VSS 11
VSS 14
20 K
20 K
RANGE
CONTROL
20 K
VSS
20 K
VSS
10
SSCC
12
S1
13
S0
6
S2
7
S3
Cypress Semiconductor Corporation
Document #: 38-07429 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 30, 2002
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