9/10
CY2509/10
Spread Aware鈩? Ten/Eleven Output Zero Delay Buffer
Features
鈥?Spread Aware
TM
鈥攄esigned to work with SSFTG refer-
ence signals
鈥?Well suited to both 100- and 133-MHz designs
鈥?Ten (CY2509) or eleven (CY2510) LVCMOS/LVTTL
outputs
鈥?Single output enable pin for CY2510 version, dual pins
on CY2509 devices allow shutting down a portion of the
outputs
鈥?3.3V power supply
鈥?On board 25鈩?damping resistors
鈥?Available in 24-pin TSSOP package
鈥?Improved tracking skew, but narrower frequency sup-
port limit when compared to W132-09B/10B
Key Specifications
Operating Voltage: ................................................ 3.3V鹵10%
Operating Range: ........................40 MHz < f
OUT
< 140 MHz
Cycle-to-Cycle Jitter: ................................................<100 ps
Output to Output Skew: ............................................<100 ps
Phase Error Jitter: .....................................................<100 ps
Block Diagram
FBIN
CLK
Pin Configurations
PLL
FBOUT
Q0
Q1
Q2
AGND
VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK
AVDD
VDD
Q9
Q8
GND
GND
Q7
Q6
Q5
VDD
FBIN
CY2510
OE0:4
Q3
OE
Q4
Q5
OE5:8
Q6
Q7
Q8
Q9
Configuration of these blocks dependent upon specific option being used
AGND
VDD
Q0
Q1
Q2
GND
GND
Q3
Q4
VDD
OE0:4
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK
AVDD
VDD
Q8
Q7
GND
GND
Q6
Q5
VDD
OE5:8
FBIN
CY2509
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
Document #: 38-07230 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 14, 2002
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