CY24130
HOTLink II鈩?SMPTE Receiver Training Clock
Features
鈥?Integrated phase-locked loop
鈥?Low-jitter, high-accuracy outputs
鈥?3.3V operation
Benefits
鈥?Internal PLL with up to 400-MHz internal operation
鈥?Meets critical timing requirements in complex system
designs
鈥?/div>
Enables application compatibility
Part Number
CY24130-1
CY24130-2
Outputs
2
2
Input Frequency
27 MHz (Driven Reference)
27 MHz (Crystal Reference)
Output Frequency Range
1 copy 27-MHz reference clock output
1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)
1 copy 27-MHz reference clock output
1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)
Logic Block Diagram
XIN
XOUT
P
PLL
REFCLK
S0
S1
S2
OSC.
Q
桅
VCO
OUTPUT
MULTIPLEXER
AND
DIVIDERS
CLKA
VDDL
VDD
AVDD AVSS VSS VSSL
Pin Configuration
CY24130-1, -2
16-pin TSSOP
XIN
VDD
AVDD
S0
AVSS
VSSL
N/C
CLKA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
XOUT
S2
REFCLK
VSS
N/C
VDDL
S1
N/C
Cypress Semiconductor Corporation
Document #: 38-07711 Rev. **
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised February 04, 2005
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