鈥?Spread Aware鈩?/div>
The CY23S08 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in
Table 1.
If all
output clocks are not required, Bank B can be three-stated.
The select inputs also allow the input clock to be directly
applied to the output for chip and system testing purposes.
The CY23S08 PLL enters a power-down state when there are
no rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
50
碌A(chǔ)
of current draw. The PLL shuts down in two additional
cases as shown in
Table 1.
Multiple CY23S08 devices can accept the same input clock
and distribute it in a system. In this case, the skew between
the outputs of two devices is guaranteed to be less than
700 ps.
The CY23S08 is available in five different configurations, as
shown in
Table 2.
The CY23S08鈥? is the base part, where the
output frequencies equal the reference if there is no counter in
the feedback path. The CY23S08鈥?H is the high-drive version
of the 鈥?, and rise and fall times on this device are much faster.
The CY23S08鈥? allows the user to obtain 2X and 1X
frequencies on each output bank. The exact configuration and
output frequencies depends on which output drives the
feedback pin. The CY23S08鈥?H is the high-drive version of
the 鈥?, and rise and fall times on this device are much faster.
The CY23S08鈥? allows the user to obtain 4X and 2X
frequencies on the outputs.
The CY23S08鈥? enables the user to obtain 2X clocks on all
outputs. Thus, the part is extremely versatile, and can be used
in a variety of applications.
Functional Description
The CY23S08 is a 3.3V zero delay buffer designed to
distribute high-speed clocks in PC, workstation, datacom,
telecom, and other high-performance applications.
The part has an on-chip PLL which locks to an input clock
presented on the REF pin. The PLL feedback is required to be
driven into the FBK pin, and can be obtained from one of the
outputs. The input-to-output propagation delay is guaranteed
to be less than 350 ps, and output-to-output skew is
guaranteed to be less than 250 ps.
Block Diagram
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REF
Pin Configuration
PLL
MUX
FBK
CLKA1
CLKA2
CLKA3
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
SOIC
Top View
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Extra Divider (鈥?, 鈥?)
S2
S1
CLKA4
FBK
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
Select Input
Decoding
/2
CLKB1
CLKB2
CLKB3
Extra Divider (鈥?, 鈥?H, 鈥?)
CLKB4
Cypress Semiconductor Corporation
Document #: 38-07265 Rev. *D
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised June 03, 2004
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