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CY23FS04ZIT Datasheet

  • CY23FS04ZIT

  • Failsafe 2.5V/ 3.3V Zero Delay Buffer

  • 12頁

  • CYPRESS

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CY23FS04
Failsafe鈩?2.5V/ 3.3V Zero Delay Buffer
Features
鈥?Internal DCXO for continuous glitch-free operation
鈥?Zero input-output propagation delay
鈥?Low-jitter (< 35 ps RMS) outputs
鈥?Low Output-to-Output skew (< 200 ps)
鈥?4.17 MHz鈥?70 MHz reference input
鈥?Supports industry standard input crystals
鈥?170 MHz outputs
鈥?5V-tolerant inputs
鈥?Phase-locked loop (PLL) Bypass Mode
鈥?Dual Reference Inputs
鈥?16-pin TSSOP
鈥?2.5V or 3.3V output power supplies
鈥?3.3V core power supply
鈥?Industrial temperature available
Functional Description
The CY23FS04 is a FailSafe錚?zero delay buffer with two
reference clock inputs and four phase-aligned outputs. The
device provides an optimum solution for applications where
continuous operation is required in the event of a primary clock
failure.
The continuous, glitch-free operation is achieved by using a
DCXO, which serves as a redundant clock source in the event
of a reference clock failure by maintaining the last frequency
and phase information of the reference clock.
The unique feature of the CY23FS04 is that the DCXO is in
fact the primary clocking source, which is synchronized
(phase-aligned) to the external reference clock. When this
external clock is restored, the DCXO automatically resynchro-
nizes to the external clock.
The frequency of the crystal, which will be connected to the
DCXO must be chosen to be an integer factor of the frequency
of the reference clock. This factor is set by two select lines:
S[2:1], please see
Table 1.
Output power supply, VDD can be
connected to either 2.5V or 3.3V. VDDC is the power supply
pin for internal circuits and must be connected to 3.3V.
Block Diagram
Pin Configuration
XIN XOUT
REFSEL
DCXO
REF1
REF2
FBK
Failsafe
TM
Block
PLL
REF1
REF2
CLKB1
CLKB2
S2
2
2
CLKA[1:2]
CLKB[1:2]
VSS
VDDC
XIN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
REFSEL
FBK
CLKA1
CLKA2
S1
VDD
FAIL#/SAFE
XOUT
16 pin TSSOP
Decoder
FAIL# /SAFE
2
CY23FS04
S[2:1]
Cypress Semiconductor Corporation
Document #: 38-07304 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
,
CA 95134
鈥?/div>
408-943-2600
Revised October 12, 2004

CY23FS04ZIT相關型號PDF文件下載

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  • 英文版
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    ETC
  • 英文版
    Stepper System Controller
    ETC [ETC]
  • 英文版
    Stepper System Controller
    ETC
  • 英文版
    Stepper System Controller
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  • 英文版
    Phase-Aligned Clock Multiplier
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  • 英文版
    Phase-Aligned Clock Multiplier
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    Frequency Multiplier and Zero Delay Buffer
    CYPRESS
  • 英文版
    Frequency Multiplier and Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    Clocks and Buffers
    ETC
  • 英文版
    Phase-Aligned Clock Multiplier
    CYPRESS
  • 英文版
    3.3V Zero Delay Buffer
    CYPRESS
  • 英文版
    3.3V Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    CY2305 and CY2309 as PCI and SDRAM Buffers
    CYPRESS
  • 英文版
    LOW-COST 3.3V ZERO DELAY BUFFER
    CYPRESS [C...
  • 英文版
    CY2305 and CY2309 as PCI and SDRAM Buffers
    CYPRESS [C...
  • 英文版
    3.3V Zero Delay Buffer
    CYPRESS
  • 英文版
    3.3V Zero Delay Buffer
    CYPRESS [C...
  • 英文版
    CY2305 and CY2309 as PCI and SDRAM Buffers
    CYPRESS
  • 英文版
    LOW-COST 3.3V ZERO DELAY BUFFER
    CYPRESS [C...
  • 英文版
    CY2305 and CY2309 as PCI and SDRAM Buffers
    CYPRESS [C...

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