鈥?/div>
335 ps max Total Timing Budget鈩?(TTB)鈩?window
2.5V or 3.3V outputs
20 LVCMOS outputs
50 MHz to 200 MHz output frequency
50 MHz to 200 MHz input frequency
Integrated phase-locked loop (PLL) with lock indicator
Spread Aware鈩⑩€攄esigned to work with SSFTG
reference signals
鈥?3.3V core power supply
鈥?Available in 48-pin TSSOP and QFN packages
Description
The CY23020-1-1 is a high-performance 200-MHz PLL-based
zero delay buffer designed for high-speed clock distribution
applications. The device features a guaranteed TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
The CY23020-1 outputs are three-state when S1 = S2 = 0 for
reduced power. When S1 = 1 and S2 = 0 the PLL is bypassed
and the CY23020-1 functions as a fan-out buffer.
Block Diagram
LOCKED
Pin Configurations
LOCK
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
9
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDC
GNDC
REF鈥?/div>
REF+
VDD
Q19
Q18
GND
Q17
Q16
VDD
Q15
Q14
GND
Q13
Q12
VDD
Q11
Q10
GND
GNDC
VDDC
C1
GND
FBOUT
REF
PLL
FBIN
Div
Q1
Q2
NC
FBIN鈥?/div>
FBIN+
VDD
FBOUT
Q1
GND
C1
C1C1
C1
S1:2
RANGE
MUL
Output
Control
Logic
Q3
Q17
Q18
Q19
VDD
Q4
Q5
GND
Q6
Q7
VDD
Q8
Q9
48
F
B
O
U
T
+
47
V
D
D
46
F
B
I
N
+
45
F
B
I
N
-
44
N
C
1
2
3
4
5
6
Q1
VSS
Q2
Q3
VDD
Q4
Q5
VSS
43
L
O
C
K
42
V
D
D
C
41
V
S
S
C
40
R
E
F
-
39
R
E
F
+
38
V
D
D
37
Q
1
9
Q 18 36
VSS 35
Q 17 34
Q 16 33
GND
S2
S1
MUL
RANGE
48-pin TSSOP
4 8 - p in Q F N
VDD 32
Q 15 31
Q 14 30
VSS
29
7
8
9
10
11
12
Q6
Q7
VDD
Q8
V
S
S
C
Q
1
0
Q 13 28
Q 12 27
VDD 26
Q 11 25
Q
9
V
S
S
S
2
S
1
M
U
L
R
A
N
G
E
18
G
N
D
C
1
V
D
D
C
V
S
S
13
14
15
16
17
19
20
21
22
23
24
Cypress Semiconductor Corporation
Document #: 38-07120 Rev. *B
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised November 5, 2002
CY23020-1
Q2
CY23020ZC-1T相關型號PDF文件下載
-
型號
版本
描述
廠商
下載
-
英文版
Stepper System Controller
ETC
-
英文版
Stepper System Controller
ETC [ETC]
-
英文版
Stepper System Controller
ETC
-
英文版
Stepper System Controller
ETC [ETC]
-
英文版
Phase-Aligned Clock Multiplier
CYPRESS
-
英文版
Phase-Aligned Clock Multiplier
CYPRESS [C...
-
英文版
Frequency Multiplier and Zero Delay Buffer
CYPRESS
-
英文版
Frequency Multiplier and Zero Delay Buffer
CYPRESS [C...
-
英文版
Clocks and Buffers
ETC
-
英文版
Phase-Aligned Clock Multiplier
CYPRESS
-
英文版
3.3V Zero Delay Buffer
CYPRESS
-
英文版
3.3V Zero Delay Buffer
CYPRESS [C...
-
英文版
CY2305 and CY2309 as PCI and SDRAM Buffers
CYPRESS
-
英文版
LOW-COST 3.3V ZERO DELAY BUFFER
CYPRESS [C...
-
英文版
CY2305 and CY2309 as PCI and SDRAM Buffers
CYPRESS [C...
-
英文版
3.3V Zero Delay Buffer
CYPRESS
-
英文版
3.3V Zero Delay Buffer
CYPRESS [C...
-
英文版
CY2305 and CY2309 as PCI and SDRAM Buffers
CYPRESS
-
英文版
LOW-COST 3.3V ZERO DELAY BUFFER
CYPRESS [C...
-
英文版
CY2305 and CY2309 as PCI and SDRAM Buffers
CYPRESS [C...
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