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CY2254A Datasheet

  • CY2254A

  • Pentium Processor Compatible Clock Synthesizer/Driver

  • 97.69KB

  • 8頁

  • CYPRESS

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4A
CY2254A
Pentium
Processor Compatible
Clock Synthesizer/Driver
Features
鈥?Multiple clock outputs to meet requirements of most
Pentium
motherboards
鈥?Four pin-selectable CPU clocks @ 66.66 MHz, 60.0
MHz, and 50.0 MHz for support of Intel Triton
鈩?/div>
PCIset
based PC
鈥?55.0 MHz pin-selectable CPU clock also available (鈭?
option only)
鈥?Six PCI clocks at 1/2 CPU Clock frequency
鈥?One I/O clock @ 24 MHz
鈥?One Keyboard Controller clock @ 12 MHz (鈭? option)
or one Universal Serial Bus clock @ 48 MHz
(鈭? option)
鈥?Two Ref. clocks @ 14.318 MHz
鈥?Ref. 14.318 MHz Xtal oscillator input
鈥?CPU clock jitter < 200 ps cycle-to-cycle
鈥?Low skew outputs
鈥?< 250 ps between CPU clocks
鈥?< 250 ps between PCI clocks
鈥?< 500 ps between CPU and PCI clocks (鈭? option)
鈥?CPU clock leads PCI clock by +1 ns min. to +4 ns
max. (鈭? option)
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Freq. stability = 0.01% (max.)
Output duty cycle 45% min. to 55% max.
Test mode support (鈭? option only)
3.3V or 5.0V operation
Internal pull-up resistors on S0, S1, and OE inputs
Functional Description
The CY2254A is a Clock Synthesizer/Driver that provides the
multiple clocks required for a Pentium-based PC. The
CY2254A has low-skew outputs (< 250 ps between the CPU
Clocks, < 250 ps between the PCI Clocks). In addition, the
CY2254A CPU clock outputs have less than 200 ps cy-
cle-to-cycle jitter. Finally, both the PCI and CPU clock outputs
meet the 1 V/ns slew rate requirement of a Pentium proces-
sor-based system.
The CY2254A accepts a 14.318 MHz reference signal as its
input. The CY2254A has 2 PLLs, one of which generates the
CPU and PCI clocks, and the other generates the I/O and Key-
board Controller or USB clocks. The CY2254A runs off either
a 3.3V or 5V supply.
The CY2254A is available in two options. The
鈭?
option sup-
ports the Intel Triton PCIset and provides a 12 MHz keyboard
clock on pin 25. The
鈭?
option provides a 48 MHz USB clock
on pin 25 and supports the Cyrix
M1 processor.
Logic Block Diagram
REF0 (14.318 MHz)
REF1 (14.318 MHz)
SYS
PLL
XTALIN
XTALOUT
14.318
MHz
OSC.
CPU
PLL
ROM
S0
S1
鈭?
option only
Pin Configuration
Top View
SOIC
V
DD
XTALIN
XTALOUT
V
SS
OE
CPUCLK0
CPUCLK1
V
DD
CPUCLK2
CPUCLK3
V
SS
S1
S0
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
REF0
REF1
V
DD
SEEBELOW
IOCLK
V
SS
PCICLK2
PCICLK3
V
DD
PCICLK4
PCICLK5
V
SS
PCICLK1
PCICLK0
2
2
KBDCLK (12 MHz)
IOCLK (24 MHz)
USBCLK (48 MHz)
CPUCLK0
CPUCLK1
CPUCLK2
CPUCLK3
2
DELAY
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
OPTION
鈭?
鈭?
PIN 25
KBDCLK
12 MHz
USBCLK
48 MHz
OE
Intel and Pentium are registered trademarks of Intel Corporation.
Triton is a trademark of Intel Corporation.
Cyrix is a registered trademark of Cyrix Corporation.
Cypress Semiconductor Corporation
Document #: 38-07203 Rev. *A
鈥?/div>
3901 North First Street
鈥?/div>
San Jose
鈥?/div>
CA 95134 鈥?408-943-2600
Revised December 14, 2002

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