鈥?/div>
Peripheral functions
鈥?A/D converter
8-bit 12-analog input, successive approximation system,
3-stage FIFO (Conversion time: 1.55碌s at 40MHz)
鈥?Serial interface
Asynchronous serial interface (UART)
128-byte buffer RAM, 3 channels
鈥?I
2
C bus interface
64-byte buffer RAM
(supports master/slave and automatic transfer mode)
鈥?Timers
8-bit timer/counter, 2 channels (with timing output)
16-bit capture timer/counter (with timing output)
16-bit timer, 4 channels, watchdog timer
鈥?PWM output circuit
14-bit PWM, 4 channels
(2 channels of binary output switch function by PPG)
鈥?Programmable pattern generator 16-bit output, 64-byte buffer RAM, 1 channel
鈥?Remote control receive circuit
8-bit pulse measurement counter, 10-stage FIFO
鈥?Parallel interface
External register interface (8-bit parallel bus), 4-chip select
33 factors, 33 vectors, multi-interruption and priority selection possible
Sleep/stop
100-pin plastic QFP (CXP972032/973032/973064)
100-pin plastic LQFP (CXP972032/973032/973064)
104-pin plastic LFLGA (CXP973064)
鈥?/div>
Piggy/evaluation chip
CXP971000
鈥?/div>
FLASH EEPROM incorporated version CXP973F064
Structure
Silicon gate CMOS IC
Perchase of Sony's I
2
C components conveys a licence under the Philips I
2
C Patent Rights to use these components
in an I
2
C system, provided that the system conforms to the I
2
C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CXP973032相關(guān)型號PDF文件下載
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