鈥?/div>
Input clock waveform
sine wave
Input Signal Amplitude
V
SIG
575 (Max.) mVp-p (at internal clamp condition)
V
SS
16
AB
15
V
DD
14
VCO
IN
13
PC
OUT
12
V
SS
11
CLK
10
PLL
V
DD
9
V
SS
20
NC
19
AB
18
V
DD
17
VCO
IN
16
PC
OUT
15
V
SS
14
NC
13
CLK
12
PLL
V
DD
11
Autobias circuit
Driver
Timing
Autobias circuit
Driver
Timing
Clamp circuit
CCD (1698bits)
847bits
Output circuit
S/H 1bit
1698bits
Output circuit
S/H 1bit
Bias
circuit
Clamp circuit
CCD (1698bits)
847bits
Output circuit
S/H 1bit
1698bits
Output circuit
S/H 1bit
Bias
circuit
1
IN
2
VG1
3
VG2
4
OUT1
(1H)
5
V
SS
6
7
8
V
SS
OUT2
V
SS
(2H) (VCO OUT)
1
NC
2
IN
3
VG1
4
VG2
5
OUT1
(1H)
6
V
SS
7
OUT2
(2H)
8
NC
9
10
V
SS
V
SS
(VCO OUT)
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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