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CXK77V3211Q-14 Datasheet

  • CXK77V3211Q-14

  • 32768-word by 32-bit High Speed Synchronous Static RAM

  • 18頁

  • SONY   SONY

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CXK77V3211Q
-12/14
32768-word by 32-bit High Speed Synchronous Static RAM
For the availability of this product, please contact the sales office.
Description
The CXK77V3211Q is a 32K
脳
32 high performance
synchronous SRAM with a 2-bit burst counter and
output register. All synchronous inputs pass through
register controlled by a positive-edge-triggered
single clock input (CLK). The synchronous inputs
include all addresses, all data inputs, chip enable
(CE), two additional chip enables for easy depth
expansion (CE2, CE2), burst control inputs (ADSC,
ADSP, ADV), four individual byte write enables
(BW1, BW2, BW3, BW4), one byte write enable
(BWE), and global write enable (SGW).
Asynchronous inputs include the output enable
(OE) and power down control (ZZ). Two mode
control pins (LBO, FT) define four different operation
modes: Linear/Interleaved burst sequence and
Flow-Thru/Pipelined operations.
WRITE cycles can be from one to four bytes wide
as controlled by BW1 through BW4 and BWE or
SGW. The output register is included on-chip and
controlled by clock, it can be activated by connecting
FT to high for high speed pipeline operation.
Burst operation can be initiated with either address
status processor (ADSP) or address status
controller (ADSC) input pins. Subsequent burst
addresses can be internally generated as controlled
by the burst advance pin (ADV). Burst order
sequence can be controlled by connecting LBO to
high for Interleaved burst order (i486/Pentium鈩? or
by connecting LBO to low for Linear burst order.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed
WRITE cycles. Individual byte enables allow
individual bytes to be written. WRITE pass through
makes written data immediately available at the
output register during READ cycle following a
WRITE as controlled by OE.
The CXK77V3211Q operates from a +3.3V power
supply and all inputs and outputs are LVTTL
compatible. The device is ideally suited for i486 and
Pentium鈩?systems and those systems which
benefit from a very wide data bus.
100 pin QFP (Plastic)
Structure
Silicon gate CMOS IC
Features
鈥?/div>
Fast address access times and High frequency
operation
Symbol
-12
-14
Flow-through
Access
12ns
14ns
Cycle
60MHz
50MHz
Pipeline
Access
7ns
8ns
Cycle
75MHz
66MHz
鈥?/div>
5V tolerant inputs except I/O pins
鈥?/div>
A FT pin for pipelined or flow-thru architecture
鈥?/div>
A LBO mode pin as burst control pin
(i486/Pentium鈩?and Linear burst sequence)
鈥?/div>
Single +3.3V
+10%
power supply
鈥?5%
鈥?/div>
Common data inputs and data outputs
鈥?/div>
All inputs and outputs are LVTTL compatible
鈥?/div>
Four Individual BYTE WRITE enables, GLOBAL
WRITE and BYTE WRITE ENABLE
鈥?/div>
Three Chip Enables for simple depth expansion
鈥?/div>
One cycle output disable for both pipelined and
flow-thru operation
鈥?/div>
Internal input registers for address, data and
control signals
鈥?/div>
Self-timed WRITE cycle
鈥?/div>
Write pass through capability
鈥?/div>
High 30pF output drive capability at rated access
time
鈥?/div>
A ZZ pin for powerdown
鈥?/div>
100-lead QFP package for high density, high
speed operation
i486/Pentium is a trademark of Intel Corp.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
鈥?鈥?/div>
E95721-PS

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