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CXK77Q18R160GB Datasheet

  • CXK77Q18R160GB

  • MEMORY-UHS Synch SRAMS 16Meg Ultra-High-Speed Synchronous SR...

  • 162.34KB

  • 23頁

  • ETC

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SONY
廬
Description
CXK77Q36R160GB / CXK77Q18R160GB
3/33/4
Preliminary
16Mb LW R-R HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)
The CXK77Q36R160GB (organized as 524,288 words by 36 bits) and the CXK77Q18R160GB (organized as 1,048,576 words
by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input
registers, high speed RAM, output registers, and a one-deep write buffer onto a single monolithic IC. Register - Register (R-R)
read operations and Late Write (LW) write operations are supported, providing a high-performance user interface.
All address and control input signals except G (Output Enable) and ZZ (Sleep Mode) are registered on the rising edge of K
(Input Clock).
During read operations, output data is driven valid from the rising edge of K, one full clock cycle after the address is registered.
During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.
The output drivers are series terminated, and the output impedance is programmable through an external impedance matching
resistor RQ. By connecting RQ between ZQ and V
SS
, the output impedance of all DQ pins can be precisely controlled.
Sleep (power down) mode control is provided through the asynchronous ZZ input. 333 MHz operation is obtained from a single
2.5V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
Features
鈥?/div>
3 Speed Bins
-3
-33
-4
Cycle Time / Access Time
3.0ns / 1.8ns
3.3ns / 1.9ns
4.0ns / 2.0ns
鈥?Single 2.5V power supply (V
DD
): 2.5V
鹵
5%
鈥?Dedicated output supply voltage (V
DDQ
): 1.5V typical
鈥?HSTL-compatible I/O interface with dedicated input reference voltage (V
REF
): 0.75V typical
鈥?Register - Register (R-R) read operations
鈥?Late Write (LW)
鈥?Full read/write coherency
鈥?Byte Write capability
鈥?Two cycle deselect
鈥?Differential input clocks (K/K)
鈥?Asynchronous output enable (G)
鈥?Programmable impedance output drivers
鈥?Sleep (power down) mode via dedicated mode pin (ZZ)
鈥?JTAG boundary scan (subset of IEEE standard 1149.1)
鈥?119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
16Mb LW R-R, rev 0.1
1 / 23
August 20, 2001

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