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CXK77P36E160GB-4E Datasheet

  • CXK77P36E160GB-4E

  • 16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or ...

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  • SONY   SONY

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SONY
廬
CXK77P36E160GB / CXK77P18E160GB
4/42/43/44
Preliminary
16Mb LW R-L HSTL High Speed Synchronous SRAMs (512K x 36 or 1M x 18)
8Mb LW R-L w/ EC HSTL High Speed Synchronous SRAMs (256K x 36 or 512K x 18)
Description
The CXK77P36E160GB (organized as 524,288 words by 36 bits) and the CXK77P18E160GB (organized as 1,048,576 words
by 18 bits) are high speed CMOS synchronous static RAMs with common I/O pins. These synchronous SRAMs integrate input
registers, high speed RAM, output latches, and a one-deep write buffer onto a single monolithic IC. Register - Latch (R-L) read
operations and Late Write (LW) write operations are supported, providing a high-performance user interface.
Two distinct R-L modes of operation are supported, selectable via the M2 mode pin. When M2 is 鈥渉igh鈥? these devices function
as conventional 16Mb R-L SRAMs, and pin 2B functions as a conventional SA address input. When M2 is 鈥渓ow鈥? these devices
function as Error-Correcting (EC) 8Mb R-L SRAMs, and pin 2B is ignored.
When Error-Correcting 8Mb R-L mode is selected, the SRAM is divided into two banks internally - a 鈥減rimary鈥?bank and a
鈥渟econdary鈥?bank. During write operations, input data is ultimately written to both banks internally (through one stage of write
pipelining). During read operations, data is read from both banks internally, and each byte of primary bank data is individually
parity-checked. If the parity of a particular byte of primary data is correct (that is, 鈥渙dd鈥?, it is driven valid externally. If the
parity of a particular byte of primary data is incorrect (that is, 鈥渆ven鈥?, it is discarded, and the corresponding byte of secondary
bank data is driven valid externally. Primary / secondary bank data selection is performed on each data byte independently.
Data read from the secondary bank is NOT parity-checked.
Data read from the write buffer is NOT parity-checked.
All address and control input signals except ZZ (Sleep Mode) are registered on the rising edge of K (Input Clock).
During read operations, output data is driven valid from the falling edge of K, one half clock cycle after the address is registered.
During write operations, input data is registered on the rising edge of K, one full clock cycle after the address is registered.
The output drivers are series terminated, and the output impedance is programmable through an external impedance matching
resistor RQ. By connecting RQ between ZQ and V
SS
, the output impedance of all DQ pins can be precisely controlled.
Sleep (power down) mode control is provided through the asynchronous ZZ input. 250 MHz operation is obtained from a single
3.3V power supply. JTAG boundary scan interface is provided using a subset of IEEE standard 1149.1 protocol.
Features
鈥?/div>
4 Speed Bins
-4 (-4A) (-4B)
-42 (-42A) (-42B)
-43 (-43A) (-43B)
-44
Cycle Time / Access Time
4.0ns / 3.9ns (3.8ns) (3.7ns)
4.2ns / 4.2ns (4.1ns) (4.0ns)
4.3ns / 4.5ns (4.4ns) (4.3ns)
4.4ns / 4.7ns
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Single 3.3V power supply (V
DD
): 3.3V
鹵
5%
Dedicated output supply voltage (V
DDQ
): 1.9V typical
HSTL-compatible I/O interface with dedicated input reference voltage (V
REF
): 0.85V typical
Register - Latch (R-L) read operations
Late Write (LW) write operations
Conventional 16Mb or Error-Correcting (EC) 8Mb mode of operation, selectable via dedicated mode pin (M2)
Full read/write coherency
Byte Write capability
One cycle deselect
Differential input clocks (K/K)
Programmable impedance output drivers
Sleep (power down) mode via dedicated mode pin (ZZ)
JTAG boundary scan (subset of IEEE standard 1149.1)
119 pin (7x17), 1.27mm pitch, 14mm x 22mm Ball Grid Array (BGA) package
16Mb LW R-L and 8Mb LW R-L w/ EC, rev 1.1
1 / 25
March 2, 2001

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