鈥?/div>
1.7碌W (typ.) / 3.3mW (typ.)
Single 3.3V supply: 3.3V鹵0.3V
Fully static memory: No clock or timing strobe
required
Equal access and cycle time
Common data input and output: three state output
Directly LVTTL compatible: All inputs and outputs
Low voltage data retention: 2.0V (min.)
400mil 44pin TSOP (type II) package
Block Diagram
A1
A0
A7
A6
A5
A4
A3
A2
A15
A14
GND
Vcc
Memory
Matrix
512
脳
1024
Row
Decoder
Memory
Matrix
512
脳
1024
Vcc
Buffer
GND
CE
UB
LB
OE
WE
Control
I/O Gate
Column
Decoder
Pre
Decoder
I/O Gate
Column
Decoder
A13
A12
A11
A10
A9
A8
I/O Buffer
I/O Buffer
Buffer
I/O1
I/O8
I/O9 I/O16
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any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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